MBX Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.067m	21.699ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	18.193us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	17.243us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	305.569us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	34.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	94.851us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	17.243us	20	20	100.00
		mbx_csr_aliasing	2.000s	34.157us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	1.817m	21.094ms	2	2	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	2.450m	13.794ms	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	22.000s	9.785ms	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	17.000s	546.753us	5	5	100.00
V2	alert_test	mbx_alert_test	2.000s	214.730us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	37.761us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	146.534us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	146.534us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	18.193us	5	5	100.00
		mbx_csr_rw	2.000s	17.243us	20	20	100.00
		mbx_csr_aliasing	2.000s	34.157us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	15.839us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	18.193us	5	5	100.00
		mbx_csr_rw	2.000s	17.243us	20	20	100.00
		mbx_csr_aliasing	2.000s	34.157us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	15.839us	20	20	100.00
V2		TOTAL			149	151	98.68
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	557.269us	20	20	100.00
		mbx_sec_cm	2.000s	40.218us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			231	233	99.14

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.58	96.75	92.07	96.71	91.52	79.74	--	97.01	86.52

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.104861271211361997159708766114243146153153636561272345578655662683502991267401
      Line 89, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @  76469637 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  76469637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 1.mbx_stress_zero_delays.85771803669496037632986102160842187499362341111054033820766599316664512918378
      Line 205, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 156864078 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 156864078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---