OTBN Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 81.829us 0 1 0.00
V1 single_binary otbn_single 1.050m 249.115us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 16.011us 5 5 100.00
V1 csr_rw otbn_csr_rw 4.000s 19.132us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 316.173us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 32.817us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 37.427us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 19.132us 20 20 100.00
otbn_csr_aliasing 6.000s 32.817us 5 5 100.00
V1 mem_walk otbn_mem_walk 43.000s 4.989ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 21.000s 129.443us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 1.267m 241.747us 0 10 0.00
V2 multi_error otbn_multi_err 15.625s 0 1 0.00
V2 back_to_back otbn_multi 1.617m 266.879us 0 10 0.00
V2 stress_all otbn_stress_all 1.917m 466.310us 0 10 0.00
V2 lc_escalation otbn_escalate 51.000s 706.307us 13 60 21.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 9.000s 25.226us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 21.000s 82.992us 0 10 0.00
V2 alert_test otbn_alert_test 7.000s 17.726us 50 50 100.00
V2 intr_test otbn_intr_test 5.000s 19.242us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 272.944us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 272.944us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 16.011us 5 5 100.00
otbn_csr_rw 4.000s 19.132us 20 20 100.00
otbn_csr_aliasing 6.000s 32.817us 5 5 100.00
otbn_same_csr_outstanding 6.000s 24.549us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 16.011us 5 5 100.00
otbn_csr_rw 4.000s 19.132us 20 20 100.00
otbn_csr_aliasing 6.000s 32.817us 5 5 100.00
otbn_same_csr_outstanding 6.000s 24.549us 20 20 100.00
V2 TOTAL 157 246 63.82
V2S mem_integrity otbn_imem_err 12.000s 153.032us 1 10 10.00
otbn_dmem_err 18.000s 73.685us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 12.000s 73.892us 0 5 0.00
otbn_controller_ispr_rdata_err 12.000s 142.540us 0 5 0.00
otbn_mac_bignum_acc_err 12.000s 143.653us 0 5 0.00
otbn_urnd_err 10.000s 35.939us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 67.144us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 25.449us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 63.672us 9 10 90.00
V2S tl_intg_err otbn_sec_cm 3.517m 2.017ms 3 5 60.00
otbn_tl_intg_err 31.000s 183.300us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 35.000s 225.324us 16 20 80.00
V2S prim_fsm_check otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 81.829us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 18.000s 73.685us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 153.032us 1 10 10.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 31.000s 183.300us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 51.000s 706.307us 13 60 21.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 153.032us 1 10 10.00
otbn_dmem_err 18.000s 73.685us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 25.226us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.144us 5 5 100.00
otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 153.032us 1 10 10.00
otbn_dmem_err 18.000s 73.685us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 25.226us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.144us 5 5 100.00
otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 51.000s 706.307us 13 60 21.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 153.032us 1 10 10.00
otbn_dmem_err 18.000s 73.685us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 25.226us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.144us 5 5 100.00
otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 10.000s 29.370us 1 12 8.33
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 23.485us 3 5 60.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.883m 525.129us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.883m 525.129us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 17.000s 58.572us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 12.000s 241.755us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 1.817m 599.357us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 1.817m 599.357us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 30.359us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.617m 266.879us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 21.000s 73.498us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 1.050m 249.115us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.517m 2.017ms 3 5 60.00
V2S TOTAL 67 163 41.10
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.650m 2.908ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 289 585 49.40

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.92 97.91 72.90 97.10 81.41 57.57 87.18 80.68 98.72

Failure Buckets