ROM_CTRL/32KB Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.620s	173.978us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.790s	576.133us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.020s	560.461us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.050s	729.742us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.080s	496.486us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.650s	151.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.020s	560.461us	20	20	100.00
		rom_ctrl_csr_aliasing	6.080s	496.486us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.390s	206.252us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.820s	660.547us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.440s	179.077us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.020s	598.632us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.850s	298.882us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.900s	547.994us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.650s	588.757us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.650s	588.757us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.790s	576.133us	5	5	100.00
		rom_ctrl_csr_rw	9.020s	560.461us	20	20	100.00
		rom_ctrl_csr_aliasing	6.080s	496.486us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.240s	563.745us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.790s	576.133us	5	5	100.00
		rom_ctrl_csr_rw	9.020s	560.461us	20	20	100.00
		rom_ctrl_csr_aliasing	6.080s	496.486us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.240s	563.745us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	40.670s	27.114ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
		rom_ctrl_tl_intg_err	1.266m	820.395us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.620s	173.978us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.620s	173.978us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.620s	173.978us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.266m	820.395us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
		rom_ctrl_kmac_err_chk	11.850s	298.882us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.118m	3.456ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	40.670s	27.114ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.971m	511.689us	1	5	20.00
V2S		TOTAL			58	65	89.23
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.917m	17.294ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			259	266	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.107022953932928723183099607410600371110726545531478381863422499978934723678704
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 3618777321 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 3618777321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.rom_ctrl_corrupt_sig_fatal_chk.36364950288960466035537564898763060992576264063093744803170424221656050111639
      Line 97, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 5974868322 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 5974868322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 2.rom_ctrl_sec_cm.60851776755996161367826744952481236522855748858271942823822231547726046280927
      Line 361, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 37547256ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 37547256ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 37547256ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 3.rom_ctrl_sec_cm.49218516560590927776991211055334577820275335338906292081694614080731959877780
      Line 120, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 7362282ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 7362282ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 7362282ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.5551462556114173376361390942450183906897742072170685881785801110531482146490
      Line 303, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 23691788ps failed at 23691788ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 23701788ps failed at 23701788ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 1.rom_ctrl_sec_cm.17628097517656388310169390452549698927616690804663869491345991681074161295230
      Line 234, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 46539028ps failed at 46539028ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 46539028ps failed at 46539028ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'