ROM_CTRL/64KB Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	13.600s	4.155ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.170s	381.828us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.410s	1.029ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.380s	296.975us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.740s	291.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.280s	1.167ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.410s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.740s	291.792us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.970s	299.254us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.850s	294.708us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	11.850s	651.088us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	55.810s	8.106ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.070s	395.579us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	14.270s	1.098ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.420s	238.691us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.420s	238.691us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.170s	381.828us	5	5	100.00
		rom_ctrl_csr_rw	13.410s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.740s	291.792us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.380s	3.250ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.170s	381.828us	5	5	100.00
		rom_ctrl_csr_rw	13.410s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.740s	291.792us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.380s	3.250ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.082m	16.922ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
		rom_ctrl_tl_intg_err	2.748m	445.275us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	13.600s	4.155ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	13.600s	4.155ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	13.600s	4.155ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.748m	445.275us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
		rom_ctrl_kmac_err_chk	17.070s	395.579us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.601m	31.954ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.082m	16.922ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.271m	3.138ms	4	5	80.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.500m	18.139ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.07	99.59	98.66	100.00	100.00	99.64	96.80	98.81

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 2.rom_ctrl_sec_cm.53170738653362883836125839528193068689415971119709091230802636253474457909241
      Line 222, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 6165930ps failed at 6165930ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6165930ps failed at 6165930ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'