RV_TIMER Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.160s	587.979us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.700s	20.788us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.780s	94.011us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.890s	1.508ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.850s	237.618us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.320s	107.956us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.780s	94.011us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	237.618us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	2.530s	10.898ms	3	20	15.00
V2	disabled	rv_timer_disabled	2.970s	2.311ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.266m	470.192ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.266m	470.192ms	10	10	100.00
V2	stress	rv_timer_stress_all	7.690s	6.441ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.830s	15.469us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.720s	30.738us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.490s	133.727us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.490s	133.727us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.700s	20.788us	5	5	100.00
		rv_timer_csr_rw	0.780s	94.011us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	237.618us	5	5	100.00
		rv_timer_same_csr_outstanding	0.930s	108.879us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.700s	20.788us	5	5	100.00
		rv_timer_csr_rw	0.780s	94.011us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	237.618us	5	5	100.00
		rv_timer_same_csr_outstanding	0.930s	108.879us	20	20	100.00
V2		TOTAL			193	210	91.90
V2S	tl_intg_err	rv_timer_sec_cm	1.140s	178.219us	5	5	100.00
		rv_timer_tl_intg_err	1.320s	107.002us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.320s	107.002us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.480s	1.370ms	2	10	20.00
V3	max_value	rv_timer_max	1.360s	547.910us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	48.270s	20.450ms	13	20	65.00
V3		TOTAL			15	40	37.50
		TOTAL			308	350	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.72	100.00	100.00	78.66	--	100.00	96.82	98.82

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 25 failures:
- Test rv_timer_min has 8 failures.
  - 0.rv_timer_min.2188447388743263229777579996478631466876445177107160450614802398135882075390
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 218943477 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6a1a8f04) == 0x1
  UVM_INFO @ 218943477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.40663229018702265424864823001128407449990695981839781852062385317549383864437
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @  54437676 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xefdae304) == 0x1
  UVM_INFO @  54437676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
- Test rv_timer_random_reset has 17 failures.
  - 0.rv_timer_random_reset.63270162702971404080669846960198286219748350120624076910253290410473492838533
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1024390722 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xab635504) == 0x1
  UVM_INFO @ 1024390722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_random_reset.2504393922383591168318479728950868937757401857704898582700124738512726156042
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 319313218 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1c2d3104) == 0x1
  UVM_INFO @ 319313218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.81347317781483596988132071290774513828508039902849433448874438837612473822783
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  48375367 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  48375367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.66216889309103289768749562912729499402827619651962622754249051092049860002513
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  45244958 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  45244958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 5 failures:
- Test rv_timer_stress_all_with_rand_reset has 5 failures.
  - 5.rv_timer_stress_all_with_rand_reset.32793955523373519867926764124126680214890327574411498079003687208738424816684
    Line 242, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4849627161 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 4849627161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.rv_timer_stress_all_with_rand_reset.110961103233254471515666228311026671676324885400431238346683231446322563838540
    Line 519, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6846439217 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 6846439217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

1.rv_timer_stress_all_with_rand_reset.72601086005770984622709323775138608917109380045985022709383692765224842246886
Line 151, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7597542835 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7597542835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.rv_timer_stress_all_with_rand_reset.99032862739377112081119548879333967554536989457028453764537369963895439062709
Line 134, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3543015770 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3543015770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---