SPI_DEVICE/1R1W Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.924m	170.972ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.800s	48.664us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.950s	206.042us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.180s	6.657ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.860s	1.875ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.860s	53.332us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.950s	206.042us	20	20	100.00
		spi_device_csr_aliasing	16.860s	1.875ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.010s	22.523us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.490s	58.806us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.190s	62.169us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	8.236us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.050s	9.022us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	15.070s	587.906us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.070s	587.906us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.840s	15.232ms	50	50	100.00
		spi_device_tpm_sts_read	1.570s	151.850us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.300s	9.711ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.940s	59.159ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.760s	7.555ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.760s	7.555ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.840s	1.898ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.840s	1.898ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.840s	1.898ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.840s	1.898ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.840s	1.898ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	18.480s	6.247ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.172m	84.287ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.172m	84.287ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.172m	84.287ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.580s	5.045ms	50	50	100.00
		spi_device_read_buffer_direct	17.860s	4.294ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.172m	84.287ms	50	50	100.00
		spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.495m	326.621ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.300s	1.725ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.300s	1.725ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.924m	170.972ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.556m	62.184ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.604m	803.978ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	15.584us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.200s	15.284us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.080s	207.100us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.080s	207.100us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.800s	48.664us	5	5	100.00
		spi_device_csr_rw	2.950s	206.042us	20	20	100.00
		spi_device_csr_aliasing	16.860s	1.875ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	439.296us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.800s	48.664us	5	5	100.00
		spi_device_csr_rw	2.950s	206.042us	20	20	100.00
		spi_device_csr_aliasing	16.860s	1.875ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	439.296us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.690s	348.686us	5	5	100.00
		spi_device_tl_intg_err	18.280s	2.165ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.280s	2.165ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.610m	60.831ms	48	50	96.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.56	71.19	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.17892045531290153752040905151730516786169567400375081924321930643551231068280
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1259056 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[49])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1259056 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1259056 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[945])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.16664447880469347510988819080920424856810328310513099009008746958689718152841
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4861385 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[17])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4861385 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4861385 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[913])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.4930747992247754731504603188306108228460016800934825917365874165451233242486
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   6837187 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d9e4c [1011011001111001001100] vs 0x0 [0])
        UVM_ERROR @   6870187 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x777d14 [11101110111110100010100] vs 0x0 [0])
        UVM_ERROR @   6930187 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb4dad2 [101101001101101011010010] vs 0x0 [0])
        UVM_ERROR @   6954187 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1957e6 [110010101011111100110] vs 0x0 [0])
        UVM_ERROR @   7023187 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa57f5a [101001010111111101011010] vs 0x0 [0])
      

• UVM_ERROR (spi_device_scoreboard.sv:1032) scoreboard [scoreboard] Compare failed, downstream item: has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 28.spi_device_flash_mode_ignore_cmds.37936493773682656197518182916242664054837350893355903024123991630232177449475
      Line 80, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 21095264123 ps: (spi_device_scoreboard.sv:1032) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
        -------------------------------------------------------------------------
        Name                               Type              Size  Value
        -------------------------------------------------------------------------
        host_item                          spi_item          -     @67769
      

• UVM_ERROR (spi_device_scoreboard.sv:2799) [scoreboard] Check failed upload_cmd_q.size == * (* [*] vs * [*]) has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 36.spi_device_flash_mode_ignore_cmds.25973782929288454237204244215104973688443984645506047862489600504263350833780
      Line 124, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 35875410667 ps: (spi_device_scoreboard.sv:2799) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size == 0 (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 35875410667 ps: (spi_device_scoreboard.sv:2800) [uvm_test_top.env.scoreboard] Check failed upload_addr_q.size == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 35875410667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---