SPI_HOST Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.950m	23.171ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	26.384us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	15.119us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	106.260us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	240.205us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	75.889us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	15.119us	20	20	100.00
		spi_host_csr_aliasing	2.000s	240.205us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	44.948us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	63.345us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	7.000s	55.751us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	36.000s	8.656ms	50	50	100.00
		spi_host_error_cmd	2.000s	44.375us	50	50	100.00
		spi_host_event	2.767m	84.203ms	50	50	100.00
V2	clock_rate	spi_host_speed	8.000s	1.440ms	50	50	100.00
V2	speed	spi_host_speed	8.000s	1.440ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	8.000s	1.440ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.433m	10.895ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	24.910us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.000s	1.440ms	50	50	100.00
V2	full_cycle	spi_host_speed	8.000s	1.440ms	50	50	100.00
V2	duplex	spi_host_smoke	1.950m	23.171ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.950m	23.171ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.633m	8.763ms	50	50	100.00
V2	spien	spi_host_spien	5.533m	37.397ms	50	50	100.00
V2	stall	spi_host_status_stall	7.617m	159.591ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	32.000s	15.055ms	49	50	98.00
V2	data_fifo_status	spi_host_overflow_underflow	36.000s	8.656ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	41.130us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	19.618us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	545.683us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	545.683us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	26.384us	5	5	100.00
		spi_host_csr_rw	2.000s	15.119us	20	20	100.00
		spi_host_csr_aliasing	2.000s	240.205us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	34.945us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	26.384us	5	5	100.00
		spi_host_csr_rw	2.000s	15.119us	20	20	100.00
		spi_host_csr_aliasing	2.000s	240.205us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	34.945us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	110.948us	20	20	100.00
		spi_host_sec_cm	2.000s	45.816us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	110.948us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.417m	82.152ms	10	10	100.00
		TOTAL			839	840	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.09	96.82	93.35	98.69	94.25	73.07	100.00	95.21	90.42

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
  • Test spi_host_idlecsbactive has 1 failures.

    • 6.spi_host_idlecsbactive.28363005227273306885985503255735328538174973187231276013133255302517404444470
      Line 164, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log

        UVM_FATAL @ 15054501549 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x349d8554, Comparison=CompareOpEq, exp_data=0x0, call_count=16
        UVM_INFO @ 15054501549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---