SRAM_CTRL/MAIN Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.444m	3.108ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	21.025us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.040s	13.458us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.320s	508.111us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.150s	23.893us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.390s	10.005ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.040s	13.458us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	23.893us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.928m	41.430ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.953m	5.134ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	24.059m	27.869ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.138m	5.401ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.162m	161.912ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.179m	71.277ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.039m	110.372ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.500m	34.208ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.778m	965.575us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.338m	22.739ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.724m	770.574us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.764m	805.207us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.672m	2.366ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	18.157m	5.130ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.170s	5.596ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.654h	950.524ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	36.356us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.430s	521.066us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.430s	521.066us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	21.025us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	13.458us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	23.893us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	97.656us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	21.025us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	13.458us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	23.893us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	97.656us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.650s	41.394ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
		sram_ctrl_tl_intg_err	4.110s	1.918ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.110s	1.918ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	18.157m	5.130ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	18.157m	5.130ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.040s	13.458us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.500m	34.208ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.500m	34.208ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.500m	34.208ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.039m	110.372ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.540s	13.508ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.650s	41.394ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.140s	10.951ms	44	50	88.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.444m	3.108ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.444m	3.108ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.500m	34.208ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.039m	110.372ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.444m	3.108ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.000s	8.067us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.234m	3.230ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

Offending 'reqfifo_rvalid' has 10 failures:
- Test sram_ctrl_mubi_enc_err has 10 failures.
  - 11.sram_ctrl_mubi_enc_err.103768562911697200528905794433541222670705690285455552225778056677376868617904
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2280859799 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2280859799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.sram_ctrl_mubi_enc_err.69278782723939483987534016402143470445210731288982841476715549270023051320253
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/21.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 672049543 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 672049543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 6 failures:
- Test sram_ctrl_readback_err has 6 failures.
  - 10.sram_ctrl_readback_err.24822132523795673581271647224353686433321998293340245963672675469999992511817
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 1371051971 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x41)
  UVM_INFO @ 1371051971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.sram_ctrl_readback_err.46045268810072387200260066169233071373969502098162917743773604580755562034201
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 693993715 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x5b)
  UVM_INFO @ 693993715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
Offending '(!$isunknown(rdata_o))' has 3 failures:
- Test sram_ctrl_sec_cm has 3 failures.
  - 0.sram_ctrl_sec_cm.95165969871428499333677112354568251042622720475505696481153590835687975615131
    Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   8536941 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8536941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.sram_ctrl_sec_cm.55513705263309948278330539014429757290209396878835578946826082650143670645935
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1691248 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1691248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

1.sram_ctrl_sec_cm.87341899186219622604609717567325021260666578410562514229460226879500513671126
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  12865453 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  12865453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.sram_ctrl_sec_cm.88054734143269325626693342753600355369394849539479289886657462282039181012159
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   8067307 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   8067307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.3008796988931640654854899059133084862114257448722978066677120335831499757600
    Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005161699 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10005161699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```