SRAM_CTRL/RET Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.040m	3.021ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.040s	23.218us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.050s	25.499us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.150s	786.670us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	24.045us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	69.263us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.050s	25.499us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	24.045us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.920s	2.708ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.200s	398.937us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	23.500m	5.152ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.962m	8.191ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.390m	22.593ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.912m	19.421ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.460s	3.937ms	50	50	100.00
V2	executable	sram_ctrl_executable	17.530m	72.059ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.592m	817.614us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.480m	88.040ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.326m	202.575us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.583m	163.003us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.663m	1.107ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	15.570m	61.286ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.210s	97.345us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.290h	271.356ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.130s	53.505us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.230s	156.434us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.230s	156.434us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.040s	23.218us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	25.499us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	24.045us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	107.029us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.040s	23.218us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	25.499us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	24.045us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	107.029us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.390s	936.732us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
		sram_ctrl_tl_intg_err	4.160s	1.641ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.160s	1.641ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.570m	61.286ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.570m	61.286ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.050s	25.499us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	17.530m	72.059ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	17.530m	72.059ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	17.530m	72.059ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.460s	3.937ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.650s	155.266us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.390s	936.732us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.630s	43.302us	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.040m	3.021ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.040m	3.021ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	17.530m	72.059ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.460s	3.937ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.040m	3.021ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.970s	3.914us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.972m	13.787ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 12 failures:

  • Test sram_ctrl_readback_err has 12 failures.

    • 2.sram_ctrl_readback_err.111751132007859835458159041407630445405809615042796714023817021387460905287538
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  95462594 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x4d)
        UVM_INFO @  95462594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.59684728402392910989440737436510153379714397183248875872939470256790096382832
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  88193624 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x50)
        UVM_INFO @  88193624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 5.sram_ctrl_mubi_enc_err.96329631470980520086189132193436501222654888561574055978416332889333228391532
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  62681222 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  62681222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 15.sram_ctrl_mubi_enc_err.103821793162953687325768260845860549751541348271686248819711842080051916756205
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  29142997 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  29142997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.111220760623858634174710856178984796179514208684435771652588160801832905922389
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10186323 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10186323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.524805201860942295014388531687391997538794106624610631126118316407957957439
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6332574 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6332574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.93809348255880598190586597811007465004096377730467079076530487989094330515486
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 211: tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth: started at 3914073ps failed at 3914073ps
            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3914073 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3914073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.105606268400824104896024338499579466990248358325276922915181899155199867954181
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4690135 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4690135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.82344057736893036782303029392616892000842933826753021284628850209784365197310
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3327150 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3327150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 9.sram_ctrl_csr_mem_rw_with_rand_reset.54729018673960437701485666801247263914802970031646114487458460124307424185465
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  51298363 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  51298363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---