UART Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.370s	6.087ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.990s	19.071us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.980s	18.967us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.450s	109.924us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.010s	102.562us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.390s	25.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.980s	18.967us	20	20	100.00
		uart_csr_aliasing	1.010s	102.562us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.787m	235.404ms	50	50	100.00
V2	parity	uart_smoke	27.370s	6.087ms	50	50	100.00
		uart_tx_rx	4.787m	235.404ms	50	50	100.00
V2	parity_error	uart_intr	12.521m	449.390ms	50	50	100.00
		uart_rx_parity_err	12.425m	142.581ms	49	50	98.00
V2	watermark	uart_tx_rx	4.787m	235.404ms	50	50	100.00
		uart_intr	12.521m	449.390ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.912m	261.160ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.517m	126.838ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.170m	129.155ms	299	300	99.67
V2	rx_frame_err	uart_intr	12.521m	449.390ms	50	50	100.00
V2	rx_break_err	uart_intr	12.521m	449.390ms	50	50	100.00
V2	rx_timeout	uart_intr	12.521m	449.390ms	50	50	100.00
V2	perf	uart_perf	18.101m	21.638ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.470s	11.407ms	50	50	100.00
V2	line_loopback	uart_loopback	24.470s	11.407ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.869m	82.492ms	7	50	14.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.619m	78.178ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	28.070s	6.050ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.085m	8.069ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.306m	160.990ms	50	50	100.00
V2	stress_all	uart_stress_all	17.108m	125.368ms	40	50	80.00
V2	alert_test	uart_alert_test	0.930s	11.057us	50	50	100.00
V2	intr_test	uart_intr_test	0.980s	13.762us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.610s	125.099us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.610s	125.099us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.990s	19.071us	5	5	100.00
		uart_csr_rw	0.980s	18.967us	20	20	100.00
		uart_csr_aliasing	1.010s	102.562us	5	5	100.00
		uart_same_csr_outstanding	1.170s	29.564us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.990s	19.071us	5	5	100.00
		uart_csr_rw	0.980s	18.967us	20	20	100.00
		uart_csr_aliasing	1.010s	102.562us	5	5	100.00
		uart_same_csr_outstanding	1.170s	29.564us	20	20	100.00
V2		TOTAL			1035	1090	94.95
V2S	tl_intg_err	uart_sec_cm	1.300s	252.094us	5	5	100.00
		uart_tl_intg_err	1.850s	191.304us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.850s	191.304us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.057m	15.906ms	88	100	88.00
V3		TOTAL			88	100	88.00
		TOTAL			1253	1320	94.92

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	99.48	98.25	74.67	--	98.14	97.12	99.57

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 24 failures:

  • Test uart_noise_filter has 18 failures.

    • 0.uart_noise_filter.25001894627732619481749788348580110000463905313915164131663565117244166009765
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1556876885 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 1556907188 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 1556937491 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 1661149508 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 1661179811 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

    • 1.uart_noise_filter.17595620124478297462502306393198244661984755563055898974020073983418653083929
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log

        UVM_ERROR @ 13387894019 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 13387937497 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 13387980975 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (67 [0x43] vs 253 [0xfd]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 13388024453 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 13388067931 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (67 [0x43] vs 59 [0x3b]) reg name: uart_reg_block.rdata
      

    • ... and 16 more failures.

  • Test uart_stress_all has 4 failures.

    • 3.uart_stress_all.104867047795940505228844572469333618877291438482812972215890466595491159292081
      Line 80, in log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_stress_all/latest/run.log

        UVM_ERROR @ 839410027 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 839420128 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 839450431 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 221 [0xdd]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 931925086 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 931935187 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

    • 5.uart_stress_all.47068956633465374802911744346165597463580648862852393970398193076220989285734
      Line 84, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all/latest/run.log

        UVM_ERROR @ 26207449203 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 26207504759 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 26207560315 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 26294172119 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 26294172119 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 2 more failures.

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 60.uart_stress_all_with_rand_reset.114129338700863415192699449580436576751344399849639728195884098912283926416622
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 289876724 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 289922179 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 289967634 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 392423204 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 392423204 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • 64.uart_stress_all_with_rand_reset.90842026446516474800539921574156979256765472899497081825095241392384968916479
      Line 162, in log /nightly/current_run/scratch/master/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12881772607 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 12881831431 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 12881890255 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 12881949079 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 12882007903 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 23 failures:

  • Test uart_stress_all has 5 failures.

    • 0.uart_stress_all.81404362300205947442189187366054584189527472117607501120692657794787604540322
      Line 101, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 702908357808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 702931957808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 702964557808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 703219357808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 703219357808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • 6.uart_stress_all.102596585158614703895761559335084444085545242561303325819014307060897621184961
      Line 141, in log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_stress_all/latest/run.log

        UVM_ERROR @ 67127167206 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 67144500574 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 67153833926 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 67161833942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 67635501556 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
      

    • ... and 3 more failures.

  • Test uart_noise_filter has 15 failures.

    • 4.uart_noise_filter.80411601811641539075736791510317500299548984873260272908745779307208072377926
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log

        UVM_ERROR @ 4403989876 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4406500060 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4407010260 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4407479644 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4407949028 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 7.uart_noise_filter.101285776726753774927100075889515453545143235162229831203534896337891669455724
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log

        UVM_ERROR @ 19864022823 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 19864022823 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 21290771079 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 21290771079 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 23680632303 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 13 more failures.

  • Test uart_stress_all_with_rand_reset has 3 failures.

    • 38.uart_stress_all_with_rand_reset.58504360614037837433458272214054064952092166646277624324350629840491005794005
      Line 122, in log /nightly/current_run/scratch/master/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14506603583 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 14506603583 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 14676269571 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/142
        UVM_INFO @ 15026851502 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/142
        UVM_ERROR @ 15346183558 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 2
      

    • 75.uart_stress_all_with_rand_reset.61358242839493286848485229650684773618859208767752423656673350201934711755046
      Line 144, in log /nightly/current_run/scratch/master/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7683520329 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7703353821 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7706603847 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7711812222 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 7779979434 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/205
      

    • ... and 1 more failures.

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 9 failures:

  • Test uart_noise_filter has 8 failures.

    • 14.uart_noise_filter.6357550330474829716611823033779864628627845183472030371854669322677518918940
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_noise_filter/latest/run.log

        UVM_ERROR @ 404960267 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 404960267 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 404960267 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 435461243 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 435482077 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (66 [0x42] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • 18.uart_noise_filter.78583574553778364802066650683307944537885480069343384879095686902978701090983
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/18.uart_noise_filter/latest/run.log

        UVM_ERROR @ 32112281023 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 32112281023 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 32112281023 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 32233654549 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 32233654549 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • ... and 6 more failures.

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 31.uart_stress_all_with_rand_reset.2532879802621299814633035392428774515181111936058135303690840326839352494278
      Line 112, in log /nightly/current_run/scratch/master/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7187795106 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 7187795106 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7187795106 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 7227875106 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 7229315106 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 4 failures:

  • Test uart_stress_all_with_rand_reset has 3 failures.

    • 14.uart_stress_all_with_rand_reset.57569047262365036790563493044306117406009409175842134568987923253891435781924
      Line 137, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6109986264 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 6109986264 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_INFO @ 6283946264 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/223
        UVM_ERROR @ 6452146264 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 6452186264 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

    • 67.uart_stress_all_with_rand_reset.44519352094549982208304896382663575057899525673995103512821353225391380376337
      Line 81, in log /nightly/current_run/scratch/master/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 739761644 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_INFO @ 742924884 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/199
        UVM_ERROR @ 819414068 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 819414068 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 819414068 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
      

    • ... and 1 more failures.

  • Test uart_noise_filter has 1 failures.

    • 48.uart_noise_filter.38324918626085041112822792823466155113538219694927987300143146272888657399068
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/48.uart_noise_filter/latest/run.log

        UVM_ERROR @ 201979000 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 201979000 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 201979000 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 201979000 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
        UVM_ERROR @ 207854047 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:

  • Test uart_rx_parity_err has 1 failures.

    • 19.uart_rx_parity_err.53990497755375548430683838206824586552130220251827755716834113092269109505804
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/19.uart_rx_parity_err/latest/run.log

        UVM_ERROR @  19947396 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 109764833552 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/7
        UVM_INFO @ 173236127161 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/7
        UVM_INFO @ 181345476713 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/7
        UVM_INFO @ 182829146347 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/7
      

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 42.uart_stress_all_with_rand_reset.48218358914555399356790492206131302489462512743201397597348217820692176031074
      Line 206, in log /nightly/current_run/scratch/master/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18037318990 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 18057574738 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 9/10
        UVM_INFO @ 18057694738 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 9/10
      

    • 50.uart_stress_all_with_rand_reset.101743370962898243090733164108918706188684743682330027013912509642299745867468
      Line 82, in log /nightly/current_run/scratch/master/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 270480028 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 276367348 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/10
        UVM_INFO @ 276387348 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 2/10
      

  • Test uart_fifo_reset has 1 failures.

    • 143.uart_fifo_reset.67136631786488050174562647859974179066540917339615454818362772867451960016457
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/143.uart_fifo_reset/latest/run.log

        UVM_ERROR @   6124288 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 2589671164 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
        UVM_INFO @ 5048374288 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
        UVM_INFO @ 12617499288 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
        UVM_INFO @ 84038811788 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 2 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 19.uart_stress_all_with_rand_reset.38231458039045237989082253836686607677229103413111262728380269446859376396966
      Line 100, in log /nightly/current_run/scratch/master/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 342015597 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_INFO @ 402965597 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/490
        UVM_INFO @ 424015597 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/490
        UVM_ERROR @ 424315597 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_INFO @ 447615597 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/490
      

  • Test uart_stress_all has 1 failures.

    • 45.uart_stress_all.83596261485782123724508850326163350236712749481972734228334976497402825145988
      Line 95, in log /nightly/current_run/scratch/master/uart-sim-vcs/45.uart_stress_all/latest/run.log

        UVM_ERROR @ 52902148588 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 52902148588 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 52913329132 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 52913341180 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 52913353228 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 25.uart_noise_filter.109327223226531818782602110896016710021118848568086633263959074589606750171874
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/25.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1270283288 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 1271252984 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 1274404496 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 1319222633 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 1319222633 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0