AES/MASKED Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	92.369us	1	1	100.00
V1	smoke	aes_smoke	5.000s	223.868us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	62.654us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	93.690us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	3.604ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	437.948us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	161.402us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	93.690us	20	20	100.00
		aes_csr_aliasing	3.000s	437.948us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	223.868us	50	50	100.00
		aes_config_error	11.000s	384.848us	50	50	100.00
		aes_stress	28.000s	1.177ms	50	50	100.00
V2	key_length	aes_smoke	5.000s	223.868us	50	50	100.00
		aes_config_error	11.000s	384.848us	50	50	100.00
		aes_stress	28.000s	1.177ms	50	50	100.00
V2	back2back	aes_stress	28.000s	1.177ms	50	50	100.00
		aes_b2b	37.000s	1.575ms	50	50	100.00
V2	backpressure	aes_stress	28.000s	1.177ms	50	50	100.00
V2	multi_message	aes_smoke	5.000s	223.868us	50	50	100.00
		aes_config_error	11.000s	384.848us	50	50	100.00
		aes_stress	28.000s	1.177ms	50	50	100.00
		aes_alert_reset	26.000s	1.239ms	49	50	98.00
V2	failure_test	aes_man_cfg_err	13.000s	820.992us	50	50	100.00
		aes_config_error	11.000s	384.848us	50	50	100.00
		aes_alert_reset	26.000s	1.239ms	49	50	98.00
V2	trigger_clear_test	aes_clear	10.000s	524.919us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	289.844us	1	1	100.00
V2	reset_recovery	aes_alert_reset	26.000s	1.239ms	49	50	98.00
V2	stress	aes_stress	28.000s	1.177ms	50	50	100.00
V2	sideload	aes_stress	28.000s	1.177ms	50	50	100.00
		aes_sideload	37.000s	1.476ms	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	1.453ms	50	50	100.00
V2	stress_all	aes_stress_all	3.583m	19.994ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	65.547us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	359.339us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	359.339us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	62.654us	5	5	100.00
		aes_csr_rw	3.000s	93.690us	20	20	100.00
		aes_csr_aliasing	3.000s	437.948us	5	5	100.00
		aes_same_csr_outstanding	3.000s	64.831us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	62.654us	5	5	100.00
		aes_csr_rw	3.000s	93.690us	20	20	100.00
		aes_csr_aliasing	3.000s	437.948us	5	5	100.00
		aes_same_csr_outstanding	3.000s	64.831us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	24.000s	1.283ms	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	156.387us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	711.928us	5	5	100.00
		aes_tl_intg_err	3.000s	393.033us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	393.033us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	26.000s	1.239ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	223.868us	50	50	100.00
		aes_stress	28.000s	1.177ms	50	50	100.00
		aes_alert_reset	26.000s	1.239ms	49	50	98.00
		aes_core_fi	19.000s	10.007ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	186.081us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	213.499us	50	50	100.00
		aes_stress	28.000s	1.177ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	28.000s	1.177ms	50	50	100.00
		aes_sideload	37.000s	1.476ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	213.499us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	213.499us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	213.499us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	213.499us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	213.499us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	28.000s	1.177ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	28.000s	1.177ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	259.084us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	259.084us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	10.095ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	259.084us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	26.000s	1.239ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_ctr_fi	3.000s	48.697us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	259.084us	50	50	100.00
		aes_control_fi	59.000s	10.126ms	273	300	91.00
		aes_cipher_fi	56.000s	10.095ms	342	350	97.71
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.000s	639.774us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.62	96.50	99.43	95.30	97.99	97.78	98.36	98.39

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_control_fi has 16 failures.
  - 29.aes_control_fi.70101086626452284298939685967969119120772119741189618351950399998638809079178
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018782729 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018782729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 75.aes_control_fi.52907572614172491895271029723762808823060327217901775321298121522990181766398
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007025143 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007025143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 11 failures.
  - 27.aes_control_fi.22654185444073472705411498766401766204619230834652426987746151290438306150025
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 31.aes_control_fi.61623022063080886375558773766559920645363912000234592168302117190566919438360
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 3 failures.
  - 93.aes_cipher_fi.63243157183168945322695211215097452227392143537318034483510258860283393912898
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 167.aes_cipher_fi.4440630130932564804164134632429790004907176915211052723165446560723736989636
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/167.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.68256790278197707503833544589032834721203788060644195669097891403039184989035
Line 963, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 639774383 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 639774383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.39796392521681055757613242206220907147515285445023548491575199598723733832847
Line 314, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 177624718 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 177624718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 18.aes_cipher_fi.31976404992825573164509595182715158561867644800808746206483647206380945384891
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005782990 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005782990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 129.aes_cipher_fi.40632930756049617673548331030273074807160002877471247477160008674003277371615
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/129.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020132549 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020132549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.34936456938308529142355992676700436360148997105346150470851764195284933388591
    Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 119575292 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 119575292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.111564249241030076410578798428423327952453793875038318311642213865099833637199
    Line 153, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 679703820 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 679703820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.24517313166814710602548144855477372208126996233200378882308631403055128521420
    Line 287, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 748746152 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 748746152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 31.aes_core_fi.109306082824320674423849369268169021690363082134810527648138489487793457107019
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007255150 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007255150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 39.aes_alert_reset.107746564409901429913210143691084759794028823886354428308183576750488255527280
    Line 3891, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/39.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 42639008 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 42599008 PS)
  UVM_ERROR @  42639008 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  42639008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```