AES/UNMASKED Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	73.808us	1	1	100.00
V1	smoke	aes_smoke	4.000s	512.584us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	108.230us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	194.346us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	409.747us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	529.374us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	85.648us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	194.346us	20	20	100.00
		aes_csr_aliasing	4.000s	529.374us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	512.584us	50	50	100.00
		aes_config_error	8.000s	58.542us	50	50	100.00
		aes_stress	3.000s	204.560us	50	50	100.00
V2	key_length	aes_smoke	4.000s	512.584us	50	50	100.00
		aes_config_error	8.000s	58.542us	50	50	100.00
		aes_stress	3.000s	204.560us	50	50	100.00
V2	back2back	aes_stress	3.000s	204.560us	50	50	100.00
		aes_b2b	7.000s	214.796us	50	50	100.00
V2	backpressure	aes_stress	3.000s	204.560us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	512.584us	50	50	100.00
		aes_config_error	8.000s	58.542us	50	50	100.00
		aes_stress	3.000s	204.560us	50	50	100.00
		aes_alert_reset	4.000s	200.522us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	57.502us	50	50	100.00
		aes_config_error	8.000s	58.542us	50	50	100.00
		aes_alert_reset	4.000s	200.522us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	65.527us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	646.045us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	200.522us	50	50	100.00
V2	stress	aes_stress	3.000s	204.560us	50	50	100.00
V2	sideload	aes_stress	3.000s	204.560us	50	50	100.00
		aes_sideload	5.000s	266.633us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	144.760us	50	50	100.00
V2	stress_all	aes_stress_all	17.000s	869.058us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	142.481us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	401.801us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	401.801us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	108.230us	5	5	100.00
		aes_csr_rw	4.000s	194.346us	20	20	100.00
		aes_csr_aliasing	4.000s	529.374us	5	5	100.00
		aes_same_csr_outstanding	3.000s	58.861us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	108.230us	5	5	100.00
		aes_csr_rw	4.000s	194.346us	20	20	100.00
		aes_csr_aliasing	4.000s	529.374us	5	5	100.00
		aes_same_csr_outstanding	3.000s	58.861us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	75.555us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	129.890us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.473ms	5	5	100.00
		aes_tl_intg_err	6.000s	388.572us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	388.572us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	200.522us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	512.584us	50	50	100.00
		aes_stress	3.000s	204.560us	50	50	100.00
		aes_alert_reset	4.000s	200.522us	50	50	100.00
		aes_core_fi	36.000s	10.002ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	97.613us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	58.680us	50	50	100.00
		aes_stress	3.000s	204.560us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	204.560us	50	50	100.00
		aes_sideload	5.000s	266.633us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	58.680us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	58.680us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	58.680us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	58.680us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	58.680us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	204.560us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	204.560us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	129.363us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	129.363us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.033ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	129.363us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	200.522us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_ctr_fi	3.000s	132.927us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	129.363us	49	50	98.00
		aes_control_fi	34.000s	10.003ms	280	300	93.33
		aes_cipher_fi	30.000s	10.033ms	325	350	92.86
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	2.412ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.28	97.69	94.80	98.80	93.23	98.07	93.33	98.08	98.59

Failure Buckets

Job timed out after * minutes has 32 failures:
- Test aes_cipher_fi has 17 failures.
  - 9.aes_cipher_fi.71057731530527627296750681800393690731123502159283821728316452673748691279944
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_cipher_fi.79542105585567889315982874524133221589247800436857614572748094956938579653196
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 25.aes_ctr_fi.74803656513312603651867659417548867559644014594024532453946635378403693243293
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 14 failures.
  - 57.aes_control_fi.86888409112553059437157962793355924872526327280419304620038410375735779967369
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 68.aes_control_fi.37866867457241064664557933012029096616155180890122606393578603186006221677718
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 71.aes_cipher_fi.77644191134584606168608833605973194464846221852055185116504208414553514579431
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10032687097 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032687097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 82.aes_cipher_fi.72709635039769552683927429923711411421182698945479500090606203895334879169295
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/82.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012594382 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012594382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.98311872880867958909238138153480691728768654835773409059146407963179592301291
Line 535, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 406345991 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 406345991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.62296167614103406723967611132493180170353904923073666880000660933535526108856
Line 859, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 264376745 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 264376745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 21.aes_control_fi.24089822559609382825724503425440798567696871266045776889430636421918683903924
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009499833 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009499833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_control_fi.11382507540688267633611014772643048585833376390681163750664658421752191566401
    Line 131, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004163521 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004163521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 6.aes_stress_all_with_rand_reset.4650914927445391080186176825787850584588281025024014670107341556000108993251
    Line 172, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 154535989 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 154535989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.56996323731739403597031472344926851143230491971123717620565970005661020564135
    Line 150, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  18048905 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  18048905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 1 failures.

48.aes_fi.57385670198999166966388311119888303467961114996357062694510134099154548418014
Line 869, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/48.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 8975390 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8964973 PS)
  UVM_ERROR @   8975390 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   8975390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_cipher_fi has 1 failures.

208.aes_cipher_fi.25962827922431179658375301992357325685953573163237334451888282019839118347690
Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/208.aes_cipher_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 4402365 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4392365 PS)
  UVM_ERROR @   4402365 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   4402365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.843942560072361969089907258956089665217280869955843778687855648680801328911
    Line 160, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  26210807 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  26210807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.106969724583862014746980134100149750198733158408633126025603521667915353076039
    Line 799, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1496549564 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1496549564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 27.aes_core_fi.22313622580180677876806834701767170451380583443020676768541144468873545611422
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016929486 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016929486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.29933107109734099124790922748773559128316698387198321676347240379961969309607
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002067631 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002067631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```