CSRNG Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	34.000s	88.628us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	124.472us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	48.981us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	2.888ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	191.522us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	80.268us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	48.981us	20	20	100.00
		csrng_csr_aliasing	5.000s	191.522us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	36.000s	80.438us	198	200	99.00
V2	alerts	csrng_alert	47.000s	4.308ms	500	500	100.00
V2	err	csrng_err	28.000s	39.771us	495	500	99.00
V2	cmds	csrng_cmds	13.850m	72.521ms	50	50	100.00
V2	life cycle	csrng_cmds	13.850m	72.521ms	50	50	100.00
V2	stress_all	csrng_stress_all	36.817m	221.303ms	48	50	96.00
V2	intr_test	csrng_intr_test	3.000s	15.070us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	259.059us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	779.523us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	779.523us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	124.472us	5	5	100.00
		csrng_csr_rw	3.000s	48.981us	20	20	100.00
		csrng_csr_aliasing	5.000s	191.522us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	276.646us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	124.472us	5	5	100.00
		csrng_csr_rw	3.000s	48.981us	20	20	100.00
		csrng_csr_aliasing	5.000s	191.522us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	276.646us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	12.000s	945.400us	5	5	100.00
		csrng_tl_intg_err	9.000s	905.155us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	26.000s	21.412us	50	50	100.00
		csrng_csr_rw	3.000s	48.981us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	47.000s	4.308ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	36.817m	221.303ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	47.000s	4.308ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	36.817m	221.303ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	47.000s	4.308ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	905.155us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
		csrng_sec_cm	12.000s	945.400us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	36.000s	80.438us	198	200	99.00
		csrng_err	28.000s	39.771us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	8.117m	6.497ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1621	1630	99.45

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.67	98.58	96.50	100.00	97.08	92.08	100.00	95.61	90.67

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 7 failures:

  • Test csrng_err has 5 failures.

    • 46.csrng_err.77602003793051634225520018260026946151379063316071004377516114671634217448833
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/46.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 8946309 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   8946309 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8946309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 326.csrng_err.105129292015411554429483095702883881907357350336502525847603168533356235241954
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/326.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 11357821 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  11357821 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11357821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test csrng_intr has 2 failures.

    • 51.csrng_intr.9597261027022668935343098415493279879729376987944273630393950313454226628435
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/51.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 53966222 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  53966222 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  53966222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 189.csrng_intr.47457779175619387345823898445577849965931116206379872164082694653038380984135
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/189.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 102747079 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 102747079 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 102747079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

  • Test csrng_stress_all has 2 failures.

    • 14.csrng_stress_all.109376621653031698904936385223004639566831087955845532149757155059965181053365
      Line 144, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log

        UVM_ERROR @ 143848927 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 143848927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 38.csrng_stress_all.113345033071587064848856265336007967263622428102944015489960987061160386347893
      Line 152, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2185734765 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2185734765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---