DMA Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.533ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.417ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.129ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	83.577us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	82.312us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	1.993ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	2.215ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	33.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	82.312us	20	20	100.00
		dma_csr_aliasing	6.000s	2.215ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.700m	24.093ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	12.533m	392.201ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	8.500m	75.067ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.500m	75.067ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	12.533m	392.201ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	9.883m	53.768ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.500m	75.067ms	3	3	100.00
V2	dma_abort	dma_abort	16.000s	1.562ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	5.200m	20.212ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	15.178us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	26.965us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	471.605us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	471.605us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	83.577us	5	5	100.00
		dma_csr_rw	2.000s	82.312us	20	20	100.00
		dma_csr_aliasing	6.000s	2.215ms	5	5	100.00
		dma_same_csr_outstanding	3.000s	141.792us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	83.577us	5	5	100.00
		dma_csr_rw	2.000s	82.312us	20	20	100.00
		dma_csr_aliasing	6.000s	2.215ms	5	5	100.00
		dma_same_csr_outstanding	3.000s	141.792us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	4.528ms	5	5	100.00
		dma_generic_stress	9.883m	53.768ms	5	5	100.00
		dma_handshake_stress	8.500m	75.067ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	10.000s	313.404us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	328.031us	20	20	100.00
		dma_sec_cm	2.000s	36.448us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.950m	18.419ms	25	25	100.00
		dma_longer_transfer	1.867m	6.567ms	5	5	100.00
		dma_stress_all_with_rand_reset	10.000s	2.347ms	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.63	97.38	95.83	96.89	95.99	77.37	92.96	95.97	79.31

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.100705875719362467736296661127366144291526566134846481164768736456272668426652
      Line 108, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2347122840ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2347122840ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---