EDN Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.350s	17.776us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	27.742us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	37.995us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.650s	678.145us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.390s	34.544us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.550s	65.046us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	37.995us	20	20	100.00
		edn_csr_aliasing	1.390s	34.544us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	5.160s	800.102us	300	300	100.00
V2	csrng_commands	edn_genbits	5.160s	800.102us	300	300	100.00
V2	genbits	edn_genbits	5.160s	800.102us	300	300	100.00
V2	interrupts	edn_intr	1.460s	20.977us	50	50	100.00
V2	alerts	edn_alert	1.770s	310.542us	200	200	100.00
V2	errs	edn_err	1.830s	35.390us	100	100	100.00
V2	disable	edn_disable	1.280s	12.738us	50	50	100.00
		edn_disable_auto_req_mode	1.600s	62.594us	50	50	100.00
V2	stress_all	edn_stress_all	5.560s	416.792us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	14.177us	50	50	100.00
V2	alert_test	edn_alert_test	1.340s	57.318us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.940s	182.722us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.940s	182.722us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	27.742us	5	5	100.00
		edn_csr_rw	0.940s	37.995us	20	20	100.00
		edn_csr_aliasing	1.390s	34.544us	5	5	100.00
		edn_same_csr_outstanding	1.190s	55.668us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	27.742us	5	5	100.00
		edn_csr_rw	0.940s	37.995us	20	20	100.00
		edn_csr_aliasing	1.390s	34.544us	5	5	100.00
		edn_same_csr_outstanding	1.190s	55.668us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	9.810s	1.039ms	5	5	100.00
		edn_tl_intg_err	3.080s	212.164us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.380s	17.855us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.770s	310.542us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.810s	1.039ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.810s	1.039ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.810s	1.039ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.810s	1.039ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.770s	310.542us	200	200	100.00
		edn_sec_cm	9.810s	1.039ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.770s	310.542us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.080s	212.164us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.247h	10.000s	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1106	1130	97.88

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.54	98.87	94.17	97.02	91.86	96.33	97.56	92.94

Failure Buckets

• Job timed out after * minutes has 23 failures:
  • Test edn_stress_all_with_rand_reset has 23 failures.

    • 0.edn_stress_all_with_rand_reset.50424712894686550588183040637918249309507088281356944973091195624617892154047
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 2.edn_stress_all_with_rand_reset.37942104100401755517893166549537845125348184778460167132842013501018246621938
      Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 21 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 29.edn_stress_all_with_rand_reset.26228651913437024059457639880414890372761538936407828981375119085739495799321
      Line 371, in log /nightly/current_run/scratch/master/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---