HMAC Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.550s	5.919ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.360s	33.931us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.250s	59.810us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.230s	320.679us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.120s	634.605us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.718m	269.987ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.250s	59.810us	20	20	100.00
		hmac_csr_aliasing	9.120s	634.605us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.263m	5.818ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.500m	6.240ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.639m	7.202ms	30	30	100.00
		hmac_test_sha384_vectors	9.143m	13.151ms	75	75	100.00
		hmac_test_sha512_vectors	8.809m	30.466ms	75	75	100.00
		hmac_test_hmac256_vectors	14.550s	367.677us	50	50	100.00
		hmac_test_hmac384_vectors	18.120s	421.039us	60	60	100.00
		hmac_test_hmac512_vectors	19.310s	1.679ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	40.800s	4.138ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.229m	13.070ms	10	10	100.00
V2	error	hmac_error	1.108m	4.977ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.466m	34.833ms	10	10	100.00
V2	save_and_restore	hmac_smoke	11.550s	5.919ms	10	10	100.00
		hmac_long_msg	1.263m	5.818ms	10	10	100.00
		hmac_back_pressure	1.500m	6.240ms	25	25	100.00
		hmac_datapath_stress	21.229m	13.070ms	10	10	100.00
		hmac_burst_wr	40.800s	4.138ms	50	50	100.00
		hmac_stress_all	34.282m	83.763ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.550s	5.919ms	10	10	100.00
		hmac_long_msg	1.263m	5.818ms	10	10	100.00
		hmac_back_pressure	1.500m	6.240ms	25	25	100.00
		hmac_datapath_stress	21.229m	13.070ms	10	10	100.00
		hmac_wipe_secret	1.466m	34.833ms	10	10	100.00
		hmac_test_sha256_vectors	4.639m	7.202ms	30	30	100.00
		hmac_test_sha384_vectors	9.143m	13.151ms	75	75	100.00
		hmac_test_sha512_vectors	8.809m	30.466ms	75	75	100.00
		hmac_test_hmac256_vectors	14.550s	367.677us	50	50	100.00
		hmac_test_hmac384_vectors	18.120s	421.039us	60	60	100.00
		hmac_test_hmac512_vectors	19.310s	1.679ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.550s	5.919ms	10	10	100.00
		hmac_long_msg	1.263m	5.818ms	10	10	100.00
		hmac_back_pressure	1.500m	6.240ms	25	25	100.00
		hmac_datapath_stress	21.229m	13.070ms	10	10	100.00
		hmac_burst_wr	40.800s	4.138ms	50	50	100.00
		hmac_error	1.108m	4.977ms	10	10	100.00
		hmac_wipe_secret	1.466m	34.833ms	10	10	100.00
		hmac_test_sha256_vectors	4.639m	7.202ms	30	30	100.00
		hmac_test_sha384_vectors	9.143m	13.151ms	75	75	100.00
		hmac_test_sha512_vectors	8.809m	30.466ms	75	75	100.00
		hmac_test_hmac256_vectors	14.550s	367.677us	50	50	100.00
		hmac_test_hmac384_vectors	18.120s	421.039us	60	60	100.00
		hmac_test_hmac512_vectors	19.310s	1.679ms	75	75	100.00
		hmac_stress_all	34.282m	83.763ms	50	50	100.00
V2	stress_all	hmac_stress_all	34.282m	83.763ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	16.248us	50	50	100.00
V2	intr_test	hmac_intr_test	0.950s	76.419us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.310s	84.937us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.310s	84.937us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.360s	33.931us	5	5	100.00
		hmac_csr_rw	1.250s	59.810us	20	20	100.00
		hmac_csr_aliasing	9.120s	634.605us	5	5	100.00
		hmac_same_csr_outstanding	2.620s	1.384ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.360s	33.931us	5	5	100.00
		hmac_csr_rw	1.250s	59.810us	20	20	100.00
		hmac_csr_aliasing	9.120s	634.605us	5	5	100.00
		hmac_same_csr_outstanding	2.620s	1.384ms	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.270s	182.056us	5	5	100.00
		hmac_tl_intg_err	4.800s	652.322us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.800s	652.322us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.550s	5.919ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.480s	126.780us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.782m	11.692ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.890s	208.363us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.17	99.95	96.80	100.00	100.00	99.83	97.61	100.00