KEYMGR Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.000s	5.311ms	50	50	100.00
V1	random	keymgr_random	1.158m	20.568ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.310s	32.884us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.590s	16.859us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.340s	1.295ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.090s	374.741us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.450s	115.845us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.590s	16.859us	20	20	100.00
		keymgr_csr_aliasing	11.090s	374.741us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.297m	8.870ms	48	50	96.00
V2	sideload	keymgr_sideload	32.090s	1.335ms	50	50	100.00
		keymgr_sideload_kmac	25.170s	3.889ms	50	50	100.00
		keymgr_sideload_aes	19.460s	2.722ms	50	50	100.00
		keymgr_sideload_otbn	29.030s	1.185ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	34.740s	2.769ms	49	50	98.00
V2	lc_disable	keymgr_lc_disable	16.430s	411.368us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.700s	308.861us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.263m	18.733ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	20.070s	16.749ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.530s	874.719us	50	50	100.00
V2	stress_all	keymgr_stress_all	11.272m	49.827ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.160s	35.944us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.360s	117.745us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.810s	135.986us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.810s	135.986us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.310s	32.884us	5	5	100.00
		keymgr_csr_rw	1.590s	16.859us	20	20	100.00
		keymgr_csr_aliasing	11.090s	374.741us	5	5	100.00
		keymgr_same_csr_outstanding	2.540s	70.682us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.310s	32.884us	5	5	100.00
		keymgr_csr_rw	1.590s	16.859us	20	20	100.00
		keymgr_csr_aliasing	11.090s	374.741us	5	5	100.00
		keymgr_same_csr_outstanding	2.540s	70.682us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
		keymgr_tl_intg_err	7.780s	5.226ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.670s	321.340us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.670s	321.340us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.670s	321.340us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.670s	321.340us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.280s	1.140ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.780s	5.226ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.670s	321.340us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.297m	8.870ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.158m	20.568ms	50	50	100.00
		keymgr_csr_rw	1.590s	16.859us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.158m	20.568ms	50	50	100.00
		keymgr_csr_rw	1.590s	16.859us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.158m	20.568ms	50	50	100.00
		keymgr_csr_rw	1.590s	16.859us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.430s	411.368us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	20.070s	16.749ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	20.070s	16.749ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.158m	20.568ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.470s	2.120ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	22.960s	1.168ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.430s	411.368us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	22.960s	1.168ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	22.960s	1.168ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	22.960s	1.168ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.950s	1.687ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	22.960s	1.168ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	17.500s	663.841us	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1081	1110	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.13	98.26	98.24	100.00	99.01	97.71	91.23

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 0.keymgr_stress_all_with_rand_reset.115098012108059177053318113586634860340486665494812596778063976575307679851978
    Line 995, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 546103626 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 546103626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.13647531054425790428897818028850732586957912541326746271868272446045726821983
    Line 254, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153077722 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 153077722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 8.keymgr_cfg_regwen.42095365079909036233999380121040322593354019211921486474741508312940087793946
    Line 471, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  27917416 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  27917416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 27.keymgr_stress_all.85767170728033317922770553738024117343775550415126622375382599090494353552176
    Line 189, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  11574493 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  11574493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_direct_to_disabled has 1 failures.
  - 42.keymgr_direct_to_disabled.23137124494920755194525864274618800590968266050207471099264325825552978696868
    Line 219, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest/run.log
```
  UVM_ERROR @   6623494 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   6623494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 5.keymgr_custom_cm.113185620279173311635379787196489183657986912939484465477046273808411858392691
    Line 249, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10661948233 ps: (keymgr_custom_cm_vseq.sv:45) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10661948233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

9.keymgr_stress_all.70445500847105967516477508780014153970782740739153152088402820566926852837519
Line 4034, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 5771823000 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1506085145468463059296855303115583848776210624126417258014937784658912529019293962900549605051484459836389552883337973691170965153709438210870616446594004 [0x1cc197418b36e900acdcd8c2a6b830358f5726b5824243f40e24abc33d8f841313067da19d71720d4bb81b6361db0baed8af572493e18d49ae3c798f9215ebd4] vs 1506085145468463059296855303115583848776210624126417258014937784658912529019293962900549605051484459836389552883337973691170965153709438210870616446594004 [0x1cc197418b36e900acdcd8c2a6b830358f5726b5824243f40e24abc33d8f841313067da19d71720d4bb81b6361db0baed8af572493e18d49ae3c798f9215ebd4]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @ 5771823000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 34.keymgr_stress_all_with_rand_reset.40650764963896098661620179054155338428311442697961975648093874966956489893054
    Line 429, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 236969190 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 236969190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 38.keymgr_cfg_regwen.111368944744399800277369605213674043199309836822325692605681205931762244382164
    Line 134, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   8751469 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   8751469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```