KEYMGR_DPE Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	5.742m	200.000ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.590s	24.198us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.650s	24.671us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	16.410s	2.374ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.590s	97.087us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.560s	179.600us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.650s	24.671us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.590s	97.087us	5	5	100.00
V1		TOTAL			102	105	97.14
V2	intr_test	keymgr_dpe_intr_test	1.150s	40.857us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.390s	21.297us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.950s	91.859us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.950s	91.859us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.590s	24.198us	5	5	100.00
		keymgr_dpe_csr_rw	1.650s	24.671us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.590s	97.087us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.700s	92.020us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.590s	24.198us	5	5	100.00
		keymgr_dpe_csr_rw	1.650s	24.671us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.590s	97.087us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.700s	92.020us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	19.540s	996.181us	5	5	100.00
		keymgr_dpe_tl_intg_err	6.270s	245.683us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.270s	144.702us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.270s	144.702us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.270s	144.702us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.270s	144.702us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.860s	1.769ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	19.540s	996.181us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	19.540s	996.181us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			307	310	99.03

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.59	97.62	90.22	63.15	75.68	94.61	97.62	17.25

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test keymgr_dpe_smoke has 1 failures.

    • 7.keymgr_dpe_smoke.111858495049670993339811913266819464892483193339387659839316843538738328777405
      Line 3047, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/7.keymgr_dpe_smoke/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:

  • Test keymgr_dpe_csr_mem_rw_with_rand_reset has 1 failures.

    • 15.keymgr_dpe_csr_mem_rw_with_rand_reset.60207475234250293494574413451622332841637297926814912071528336317213704382269
      Line 84, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  13837911 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
        UVM_INFO @  13837911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_dpe_smoke has 1 failures.

    • 33.keymgr_dpe_smoke.52748229529059449769376549385666244570344328278207140686270596753267075518531
      Line 193, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/33.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @  21421184 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  21421184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---