KMAC/MASKED Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.294m	1.983ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.600s	104.572us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.590s	44.376us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.610s	969.539us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.600s	631.503us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.150s	76.742us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.590s	44.376us	20	20	100.00
		kmac_csr_aliasing	10.600s	631.503us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.120s	19.577us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.950s	41.867us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.291m	131.819ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.817m	40.817ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.393m	36.709ms	5	5	100.00
		kmac_test_vectors_sha3_256	36.028m	630.334ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.152m	14.180ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.332m	123.893ms	5	5	100.00
		kmac_test_vectors_shake_128	43.649m	427.008ms	5	5	100.00
		kmac_test_vectors_shake_256	44.546m	87.031ms	5	5	100.00
		kmac_test_vectors_kmac	2.980s	121.342us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.840s	281.335us	5	5	100.00
V2	sideload	kmac_sideload	7.617m	42.232ms	50	50	100.00
V2	app	kmac_app	6.343m	43.562ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.363m	23.124ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.616m	62.070ms	50	50	100.00
V2	error	kmac_error	8.950m	20.828ms	50	50	100.00
V2	key_error	kmac_key_error	16.570s	1.769ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.040s	147.293us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.310s	19.553ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.840s	588.094us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.343m	32.893ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	21.240s	350.295us	50	50	100.00
V2	stress_all	kmac_stress_all	36.587m	121.552ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.230s	99.278us	50	50	100.00
V2	alert_test	kmac_alert_test	1.290s	56.124us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.950s	165.174us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.950s	165.174us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.600s	104.572us	5	5	100.00
		kmac_csr_rw	1.590s	44.376us	20	20	100.00
		kmac_csr_aliasing	10.600s	631.503us	5	5	100.00
		kmac_same_csr_outstanding	3.220s	113.282us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.600s	104.572us	5	5	100.00
		kmac_csr_rw	1.590s	44.376us	20	20	100.00
		kmac_csr_aliasing	10.600s	631.503us	5	5	100.00
		kmac_same_csr_outstanding	3.220s	113.282us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.840s	96.195us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.840s	96.195us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.840s	96.195us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.840s	96.195us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.500s	868.613us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.696m	24.721ms	5	5	100.00
		kmac_tl_intg_err	5.050s	486.404us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.050s	486.404us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	21.240s	350.295us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.294m	1.983ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.617m	42.232ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.840s	96.195us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.696m	24.721ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.696m	24.721ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.696m	24.721ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.294m	1.983ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	21.240s	350.295us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.696m	24.721ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.410m	35.402ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.294m	1.983ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.657m	48.062ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.15	99.27	94.45	99.89	79.58	97.15	97.83	97.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.48515391667413218626662206068878044674589262103027118697979525736205886118624
    Line 218, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2055983377 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 2055983377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.kmac_stress_all_with_rand_reset.6540500038404888625837837717894208169880689187567520800323398720772918131693
    Line 278, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1901953004 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 1901953004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *

has 2 failures:

Test kmac_stress_all has 2 failures.

36.kmac_stress_all.44351506950165130137000694458947531931788839736535728158557343613376056605553
Line 495, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log

  UVM_ERROR @ 138130595135 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 138130595135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.kmac_stress_all.39534827891485161646222005309837978133727101285866513684684284858286939034483
Line 582, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/39.kmac_stress_all/latest/run.log

  UVM_ERROR @ 73917417906 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 73917417906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---