KMAC/UNMASKED Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.020m	3.720ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	198.926us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.360s	119.916us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.140s	2.094ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.670s	1.523ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.040s	36.826us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.360s	119.916us	20	20	100.00
		kmac_csr_aliasing	6.670s	1.523ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.020s	110.843us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.280s	184.210us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.581m	124.363ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.964m	77.607ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.076m	62.753ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.269m	156.628ms	5	5	100.00
		kmac_test_vectors_sha3_384	15.686m	25.557ms	5	5	100.00
		kmac_test_vectors_sha3_512	16.883m	197.091ms	5	5	100.00
		kmac_test_vectors_shake_128	37.546m	604.978ms	5	5	100.00
		kmac_test_vectors_shake_256	31.245m	60.657ms	5	5	100.00
		kmac_test_vectors_kmac	2.290s	204.024us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.960s	320.095us	5	5	100.00
V2	sideload	kmac_sideload	7.250m	23.353ms	50	50	100.00
V2	app	kmac_app	5.374m	12.848ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.687m	72.947ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.224m	18.317ms	50	50	100.00
V2	error	kmac_error	5.821m	101.206ms	50	50	100.00
V2	key_error	kmac_key_error	18.230s	17.460ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	34.400s	10.081ms	46	50	92.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.550s	2.376ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.440s	7.944ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.456m	30.771ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.740s	1.007ms	50	50	100.00
V2	stress_all	kmac_stress_all	29.629m	214.697ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	45.195us	50	50	100.00
V2	alert_test	kmac_alert_test	1.300s	196.468us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.990s	885.942us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.990s	885.942us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	198.926us	5	5	100.00
		kmac_csr_rw	1.360s	119.916us	20	20	100.00
		kmac_csr_aliasing	6.670s	1.523ms	5	5	100.00
		kmac_same_csr_outstanding	2.290s	1.131ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	198.926us	5	5	100.00
		kmac_csr_rw	1.360s	119.916us	20	20	100.00
		kmac_csr_aliasing	6.670s	1.523ms	5	5	100.00
		kmac_same_csr_outstanding	2.290s	1.131ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.850s	77.034us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.850s	77.034us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.850s	77.034us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.850s	77.034us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.800s	954.684us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	53.970s	19.010ms	5	5	100.00
		kmac_tl_intg_err	3.420s	719.227us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.420s	719.227us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.740s	1.007ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.020m	3.720ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.250m	23.353ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.850s	77.034us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.970s	19.010ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.970s	19.010ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.970s	19.010ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.020m	3.720ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.740s	1.007ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.970s	19.010ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.029m	43.531ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.020m	3.720ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.438m	9.801ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			934	940	99.36

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.59	97.69	94.41	100.00	72.73	96.04	97.74	96.55

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 10.kmac_sideload_invalid.61456811039054251622355994903084391676204680249463968489856054177243801783858
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10219822513 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb188d000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10219822513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 32.kmac_sideload_invalid.20158012910802724603453998105169188914350586723135218034518281039305749468292
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10350057908 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4bdcf000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10350057908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 1.kmac_sideload_invalid.94415417434760724667238183295352244247998649559670849733327586909716585134698
      Line 91, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10442164916 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c15c000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
        UVM_INFO @ 10442164916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 4.kmac_stress_all_with_rand_reset.66925652759036508934809821972840378586473526437025342839169626775121362787341
      Line 238, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3925813472 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3925813472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 21.kmac_sideload_invalid.102965645443006438875003141564572768349710261081152732171802489754663157797692
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10081413767 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x720e7000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10081413767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 26.kmac_key_error.70697998726254498342331299728402061825700745131258582826547887364184966462937
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/26.kmac_key_error/latest/run.log

        UVM_ERROR @ 949110881 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 949110881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---