MBX Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.483m	4.301ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	77.593us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	27.812us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	6.000s	897.630us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	35.855us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	161.122us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	27.812us	20	20	100.00
		mbx_csr_aliasing	2.000s	35.855us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	1.650m	4.644ms	1	2	50.00
V2	mbx_max_activity	mbx_stress_zero_delays	1.333m	4.031ms	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	10.000s	2.900ms	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	20.000s	1.221ms	5	5	100.00
V2	alert_test	mbx_alert_test	2.000s	62.904us	50	50	100.00
V2	intr_test	mbx_intr_test	3.000s	131.161us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	5.000s	51.483us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	5.000s	51.483us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	77.593us	5	5	100.00
		mbx_csr_rw	2.000s	27.812us	20	20	100.00
		mbx_csr_aliasing	2.000s	35.855us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	102.106us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	77.593us	5	5	100.00
		mbx_csr_rw	2.000s	27.812us	20	20	100.00
		mbx_csr_aliasing	2.000s	35.855us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	102.106us	20	20	100.00
V2		TOTAL			148	151	98.01
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	386.001us	20	20	100.00
		mbx_sec_cm	2.000s	17.997us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			230	233	98.71

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.55	96.68	91.89	96.64	91.79	79.74	--	97.01	86.52

Failure Buckets

UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register

has 3 failures:

Test mbx_stress has 1 failures.

0.mbx_stress.48929924330120856743630383870963709437384749604360920109536080212686388661173
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

  UVM_ERROR @  11072966 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
  UVM_INFO @  11072966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test mbx_stress_zero_delays has 1 failures.

1.mbx_stress_zero_delays.32649301396568897923189491481055273073441970468411757841869301107078901744833
Line 89, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

  UVM_ERROR @  17910811 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
  UVM_INFO @  17910811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test mbx_imbx_oob has 1 failures.

1.mbx_imbx_oob.52721579233368336269815975974483833664292091674095471720248149348371286507267
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest/run.log

  UVM_ERROR @  13890417 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
  UVM_INFO @  13890417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---