OTBN Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 13.000s 294.830us 0 1 0.00
V1 single_binary otbn_single 1.867m 1.740ms 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 7.000s 59.055us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 24.401us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 100.118us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 22.366us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 15.000s 51.719us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 24.401us 20 20 100.00
otbn_csr_aliasing 6.000s 22.366us 5 5 100.00
V1 mem_walk otbn_mem_walk 57.000s 3.296ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 25.000s 377.184us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 51.000s 198.611us 0 10 0.00
V2 multi_error otbn_multi_err 50.000s 1.091ms 0 1 0.00
V2 back_to_back otbn_multi 6.433m 1.402ms 0 10 0.00
V2 stress_all otbn_stress_all 1.133m 1.943ms 0 10 0.00
V2 lc_escalation otbn_escalate 36.000s 133.764us 11 60 18.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 11.000s 67.502us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 13.000s 109.744us 0 10 0.00
V2 alert_test otbn_alert_test 9.000s 141.130us 50 50 100.00
V2 intr_test otbn_intr_test 9.000s 33.901us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 191.064us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 191.064us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 7.000s 59.055us 5 5 100.00
otbn_csr_rw 8.000s 24.401us 20 20 100.00
otbn_csr_aliasing 6.000s 22.366us 5 5 100.00
otbn_same_csr_outstanding 6.000s 87.042us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 7.000s 59.055us 5 5 100.00
otbn_csr_rw 8.000s 24.401us 20 20 100.00
otbn_csr_aliasing 6.000s 22.366us 5 5 100.00
otbn_same_csr_outstanding 6.000s 87.042us 20 20 100.00
V2 TOTAL 155 246 63.01
V2S mem_integrity otbn_imem_err 11.000s 65.488us 2 10 20.00
otbn_dmem_err 19.000s 66.576us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 17.000s 37.859us 0 5 0.00
otbn_controller_ispr_rdata_err 12.000s 76.064us 0 5 0.00
otbn_mac_bignum_acc_err 12.000s 97.027us 0 5 0.00
otbn_urnd_err 5.000s 25.168us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 373.424us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 10.000s 80.225us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 108.152us 8 10 80.00
V2S tl_intg_err otbn_sec_cm 3.350m 3.141ms 2 5 40.00
otbn_tl_intg_err 48.000s 240.013us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 33.000s 344.864us 18 20 90.00
V2S prim_fsm_check otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S prim_count_check otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_mem_scramble otbn_smoke 13.000s 294.830us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 19.000s 66.576us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 65.488us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 48.000s 240.013us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 36.000s 133.764us 11 60 18.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 65.488us 2 10 20.00
otbn_dmem_err 19.000s 66.576us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 67.502us 4 5 80.00
otbn_illegal_mem_acc 7.000s 373.424us 5 5 100.00
otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_scramble_key_sideload otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 65.488us 2 10 20.00
otbn_dmem_err 19.000s 66.576us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 67.502us 4 5 80.00
otbn_illegal_mem_acc 7.000s 373.424us 5 5 100.00
otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 36.000s 133.764us 11 60 18.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 65.488us 2 10 20.00
otbn_dmem_err 19.000s 66.576us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 67.502us 4 5 80.00
otbn_illegal_mem_acc 7.000s 373.424us 5 5 100.00
otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 8.000s 77.510us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 13.832s 4 5 80.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 50.000s 359.123us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 50.000s 359.123us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 113.694us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 13.000s 64.588us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 1.067m 4.272ms 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 1.067m 4.272ms 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 11.000s 42.909us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 6.433m 1.402ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 1.233m 273.686us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 1.867m 1.740ms 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.350m 3.141ms 2 5 40.00
V2S TOTAL 68 163 41.72
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 9.400m 6.184ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 288 585 49.23

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.94 97.93 73.16 97.17 78.48 57.70 87.18 80.68 98.72

Failure Buckets