ROM_CTRL/32KB Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.170s	417.385us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.060s	796.679us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.110s	173.209us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.260s	537.092us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.360s	131.273us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.180s	649.561us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.110s	173.209us	20	20	100.00
		rom_ctrl_csr_aliasing	5.360s	131.273us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.480s	172.641us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.390s	167.272us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.740s	310.630us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	25.940s	1.089ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.070s	741.937us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.190s	1.025ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.110s	636.522us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.110s	636.522us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.060s	796.679us	5	5	100.00
		rom_ctrl_csr_rw	7.110s	173.209us	20	20	100.00
		rom_ctrl_csr_aliasing	5.360s	131.273us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.610s	319.794us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.060s	796.679us	5	5	100.00
		rom_ctrl_csr_rw	7.110s	173.209us	20	20	100.00
		rom_ctrl_csr_aliasing	5.360s	131.273us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.610s	319.794us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	28.770s	3.314ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
		rom_ctrl_tl_intg_err	58.390s	955.946us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.170s	417.385us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.170s	417.385us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.170s	417.385us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	58.390s	955.946us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
		rom_ctrl_kmac_err_chk	8.070s	741.937us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.881m	20.034ms	14	20	70.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	28.770s	3.314ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.764m	2.823ms	0	5	0.00
V2S		TOTAL			54	65	83.08
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.067m	15.430ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			255	266	95.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 6 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 6 failures.
  - 0.rom_ctrl_corrupt_sig_fatal_chk.10104517948299754420448713413392632412660210234733769703371636937011643452080
    Line 81, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 367537384 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 367537384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rom_ctrl_corrupt_sig_fatal_chk.35676513472585584896478688363435153073798075471573824898209621533318963614913
    Line 91, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 4516386070 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 4516386070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

0.rom_ctrl_sec_cm.67912907529696267251765500714586530506763479587556477681234824359491419121044
Line 162, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 55997075ps failed at 55997075ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 55997075ps failed at 55997075ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

3.rom_ctrl_sec_cm.95688179121184996512679113896768917747716488795247856815953887521114194485155
Line 235, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 63451994ps failed at 63451994ps
      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 63451994ps failed at 63451994ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

2.rom_ctrl_sec_cm.38878800707108501650998621573205421893837632326331638533923767737552141693142
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 12781276ps failed at 12781276ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 12781276ps failed at 12781276ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

4.rom_ctrl_sec_cm.61780189911728234201963166317795932255469583997956559028604620433626978259750
Line 241, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 125836303ps failed at 125836303ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 125836303ps failed at 125836303ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

1.rom_ctrl_sec_cm.57579477079544725617304172824940223182528768216335954317293792478271171586392
Line 361, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 36951385ps failed at 36951385ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 40601386ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 40601386ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))