ROM_CTRL/64KB Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	13.370s	381.507us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.520s	744.645us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.900s	303.622us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.650s	306.158us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.980s	298.844us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.070s	311.081us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.900s	303.622us	20	20	100.00
		rom_ctrl_csr_aliasing	9.980s	298.844us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.390s	303.605us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.620s	213.400us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.270s	536.990us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.170m	4.066ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.570s	383.868us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.480s	4.531ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.220s	291.602us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.220s	291.602us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.520s	744.645us	5	5	100.00
		rom_ctrl_csr_rw	11.900s	303.622us	20	20	100.00
		rom_ctrl_csr_aliasing	9.980s	298.844us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.210s	1.055ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.520s	744.645us	5	5	100.00
		rom_ctrl_csr_rw	11.900s	303.622us	20	20	100.00
		rom_ctrl_csr_aliasing	9.980s	298.844us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.210s	1.055ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.045m	6.977ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
		rom_ctrl_tl_intg_err	2.393m	2.156ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	13.370s	381.507us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	13.370s	381.507us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	13.370s	381.507us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.393m	2.156ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
		rom_ctrl_kmac_err_chk	16.570s	383.868us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.693m	5.482ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.045m	6.977ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.784m	1.818ms	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.299m	20.708ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 4 failures:
  • Test rom_ctrl_sec_cm has 4 failures.

    • 0.rom_ctrl_sec_cm.1676297661824556830399615602179994144867914904808351564293686589877426745531
      Line 236, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 64122353ps failed at 64122353ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 64122353ps failed at 64122353ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 1.rom_ctrl_sec_cm.66566096189191619232014781895124180252682962825272125249837611558625203427136
      Line 305, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 37872847ps failed at 37872847ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 37872847ps failed at 37872847ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 2 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.108238446440539740770608005319447558460162491452421598567636235187070327046671
      Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 42801025ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 42801025ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 42801025ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))