RV_TIMER Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.740s	732.931us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	18.536us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.750s	17.576us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.670s	532.339us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.860s	20.018us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.370s	104.405us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.750s	17.576us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	20.018us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	2.990s	1.742ms	4	20	20.00
V2	disabled	rv_timer_disabled	3.780s	2.620ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	18.762m	2.686s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	18.762m	2.686s	10	10	100.00
V2	stress	rv_timer_stress_all	6.640s	11.942ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.880s	15.991us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.820s	14.623us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.570s	1.815ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.570s	1.815ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	18.536us	5	5	100.00
		rv_timer_csr_rw	0.750s	17.576us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	20.018us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	114.528us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	18.536us	5	5	100.00
		rv_timer_csr_rw	0.750s	17.576us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	20.018us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	114.528us	20	20	100.00
V2		TOTAL			194	210	92.38
V2S	tl_intg_err	rv_timer_sec_cm	1.330s	1.901ms	5	5	100.00
		rv_timer_tl_intg_err	1.390s	496.933us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.390s	496.933us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.310s	1.414ms	3	10	30.00
V3	max_value	rv_timer_max	1.970s	42.241us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	53.060s	11.977ms	16	20	80.00
V3		TOTAL			19	40	47.50
		TOTAL			313	350	89.43

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.72	100.00	100.00	78.66	--	100.00	96.82	98.82

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 23 failures:
- Test rv_timer_min has 7 failures.
  - 0.rv_timer_min.3083687077665649505924132173849176133966947022670667957924606743877157605449
    Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 1413969109 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfe32b504) == 0x1
  UVM_INFO @ 1413969109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.4910789598034442058560495948425382866368082085302284150907379839410300232011
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 577389821 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x33211d04) == 0x1
  UVM_INFO @ 577389821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
- Test rv_timer_random_reset has 16 failures.
  - 0.rv_timer_random_reset.24781283241113476605287245689904774082662868457613119393975908427735579383396
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1239242403 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb8282504) == 0x1
  UVM_INFO @ 1239242403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.34747212865449080376638632370452133074441197291327292615493687544495166325143
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 528400319 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xeea70f04) == 0x1
  UVM_INFO @ 528400319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.34477387385325308987073945431207330529995224870147480721838612367401334635005
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  48416019 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  48416019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.105034131781644994631218648315318181395508116159712136937791505480136489333528
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  89249709 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  89249709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 0.rv_timer_stress_all_with_rand_reset.59615935023210426369666942521138851234093633845742439121928251677466425320412
    Line 104, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3178601873 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3178601873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.rv_timer_stress_all_with_rand_reset.101257204497096479050118839726819011479734793044244250736001722119820184855238
    Line 80, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3588039078 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3588039078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

16.rv_timer_stress_all_with_rand_reset.108153218113042862640613836946216388227082478552422703376757031291065974828542
Line 165, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1706850852 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1706850852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.rv_timer_stress_all_with_rand_reset.25572711873900759516891877975340485257665327007468502016756998579539221029129
Line 121, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  23779481 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  23779481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 3.rv_timer_max.22147089081482437344725076345056522479054795322281813445777870405668250062473
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_max/latest/run.log
```
  UVM_ERROR @  42240625 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @  42240625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```