SPI_DEVICE/1R1W Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.173m	381.876ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.840s	214.090us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	400.862us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.480s	6.718ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.970s	1.243ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.080s	153.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	400.862us	20	20	100.00
		spi_device_csr_aliasing	19.970s	1.243ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	11.232us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.530s	59.170us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	21.789us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	1.340us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.900s	6.863us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.580s	303.334us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.580s	303.334us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.850s	16.266ms	50	50	100.00
		spi_device_tpm_sts_read	1.630s	162.146us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.210s	11.966ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.290s	36.619ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.620s	69.200ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.620s	69.200ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	20.500s	2.488ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	20.500s	2.488ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	20.500s	2.488ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	20.500s	2.488ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	20.500s	2.488ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	59.190s	17.982ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.258m	42.018ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.258m	42.018ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.258m	42.018ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	38.450s	3.489ms	50	50	100.00
		spi_device_read_buffer_direct	17.980s	1.716ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.258m	42.018ms	50	50	100.00
		spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.079m	297.495ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.880s	3.195ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.880s	3.195ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.173m	381.876ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.511m	49.697ms	49	50	98.00
V2	stress_all	spi_device_stress_all	9.522m	313.821ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	42.359us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.160s	16.709us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.630s	447.201us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.630s	447.201us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.840s	214.090us	5	5	100.00
		spi_device_csr_rw	2.750s	400.862us	20	20	100.00
		spi_device_csr_aliasing	19.970s	1.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	59.334us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.840s	214.090us	5	5	100.00
		spi_device_csr_rw	2.750s	400.862us	20	20	100.00
		spi_device_csr_aliasing	19.970s	1.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	59.334us	20	20	100.00
V2		TOTAL			938	961	97.61
V2S	tl_intg_err	spi_device_sec_cm	1.870s	96.466us	5	5	100.00
		spi_device_tl_intg_err	18.120s	855.233us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.120s	855.233us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.881m	82.160ms	50	50	100.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.56	71.19	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.39437062651458476211917133193649264315512801748381866813697556426387210583022
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    880967 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[47])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    880967 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    880967 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.74506282587765565131850273361294797797701918358469681972044620023756107120098
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   8566870 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[96])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   8566870 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   8566870 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

  • Test spi_device_flash_all has 1 failures.

    • 23.spi_device_flash_all.56360044676753795013940042657365334626576781321386737372583611189891821083645
      Line 104, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 3412644681 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14717952 [0xe09400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xe09400 != exp 0x0
        UVM_INFO @ 3653772450 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/10
        UVM_INFO @ 3653772450 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/10
        UVM_INFO @ 4109037653 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 9/10
        UVM_INFO @ 4130941702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

  • Test spi_device_flash_and_tpm_min_idle has 1 failures.

    • 39.spi_device_flash_and_tpm_min_idle.55008472249637510062565270653892065950931342636842485846839336971689313330370
      Line 80, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest/run.log

        UVM_ERROR @ 113688706882 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (15924224 [0xf2fc00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xf2fc00 != exp 0x0
        UVM_INFO @ 134493306882 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/11
        UVM_INFO @ 144291164882 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/11
        UVM_INFO @ 144291164882 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/11
        tl_ul_fuzzy_flash_status_q[i] = 0xa59360
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.18710135059839577835682465127984555798396143146038334020491512744701145983149
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4504515 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xab6410 [101010110110010000010000] vs 0x0 [0])
        UVM_ERROR @   4537515 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc747ca [110001110100011111001010] vs 0x0 [0])
        UVM_ERROR @   4555515 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xce8db1 [110011101000110110110001] vs 0x0 [0])
        UVM_ERROR @   4635515 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72e253 [11100101110001001010011] vs 0x0 [0])
        UVM_ERROR @   4694515 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ee6a4 [1111101110011010100100] vs 0x0 [0])