SPI_HOST Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.250m	20.047ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	20.541us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	38.123us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	59.555us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	18.000us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	121.645us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	38.123us	20	20	100.00
		spi_host_csr_aliasing	2.000s	18.000us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	31.555us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	76.976us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	22.918us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	51.000s	6.088ms	50	50	100.00
		spi_host_error_cmd	2.000s	42.868us	50	50	100.00
		spi_host_event	6.017m	12.185ms	50	50	100.00
V2	clock_rate	spi_host_speed	43.000s	10.020ms	49	50	98.00
V2	speed	spi_host_speed	43.000s	10.020ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	43.000s	10.020ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	1.333m	4.788ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	21.734us	50	50	100.00
V2	cpol_cpha	spi_host_speed	43.000s	10.020ms	49	50	98.00
V2	full_cycle	spi_host_speed	43.000s	10.020ms	49	50	98.00
V2	duplex	spi_host_smoke	1.250m	20.047ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.250m	20.047ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.317m	1.980ms	50	50	100.00
V2	spien	spi_host_spien	3.667m	25.031ms	50	50	100.00
V2	stall	spi_host_status_stall	16.467m	914.505ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	15.000s	8.551ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	51.000s	6.088ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	15.752us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	19.179us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	938.251us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	938.251us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	20.541us	5	5	100.00
		spi_host_csr_rw	2.000s	38.123us	20	20	100.00
		spi_host_csr_aliasing	2.000s	18.000us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	251.447us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	20.541us	5	5	100.00
		spi_host_csr_rw	2.000s	38.123us	20	20	100.00
		spi_host_csr_aliasing	2.000s	18.000us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	251.447us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	192.984us	20	20	100.00
		spi_host_sec_cm	2.000s	76.294us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	192.984us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.833m	40.215ms	9	10	90.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.12	96.87	93.45	98.69	94.25	73.07	100.00	95.21	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 2.spi_host_upper_range_clkdiv.103356065475848377920383235140355376000516191370652962142319568537405668982264
      Line 140, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 10.spi_host_status_stall.8557178617335719114345192202105099104348626442992232669003753517357407348631
      Line 836, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log

        UVM_ERROR @ 164608777 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
        UVM_INFO @ 164608777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 31.spi_host_speed.104012779336400537465852884916281808480065931731967829010360805545252536986015
      Line 246, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/31.spi_host_speed/latest/run.log

        UVM_FATAL @ 10020312582 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x7f22aed4, Comparison=CompareOpEq, exp_data=0x0, call_count=36
        UVM_INFO @ 10020312582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---