SRAM_CTRL/MAIN Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.702m	1.324ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	47.371us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	20.933us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	45.762us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.120s	25.892us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.020s	6.895ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	20.933us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	25.892us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.015m	71.833ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.092m	33.545ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.170m	118.578ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.131m	6.148ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	41.485m	460.104ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.153m	38.731ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.887m	208.884ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.331m	92.491ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.569m	555.806us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.461m	94.233ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.789m	799.141us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.781m	1.603ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.691m	1.436ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.783m	30.042ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.970s	1.345ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.995h	476.048ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.070s	48.147us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.390s	144.507us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.390s	144.507us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	47.371us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	20.933us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	25.892us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.180s	46.376us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	47.371us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	20.933us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	25.892us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.180s	46.376us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.057m	7.511ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
		sram_ctrl_tl_intg_err	3.810s	2.024ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.810s	2.024ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.783m	30.042ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.783m	30.042ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	20.933us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.331m	92.491ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.331m	92.491ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.331m	92.491ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.887m	208.884ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.850s	6.651ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.057m	7.511ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.050s	5.988ms	42	50	84.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.702m	1.324ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.702m	1.324ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.331m	92.491ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.887m	208.884ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.702m	1.324ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.010s	10.175us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.032m	3.388ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1167	1190	98.07

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• Offending 'reqfifo_rvalid' has 10 failures:
  • Test sram_ctrl_mubi_enc_err has 10 failures.

    • 1.sram_ctrl_mubi_enc_err.85903531331895019348628882594390481562446406653276054494002946437196469441031
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 661795392 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 661795392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.71183433458523021209566927168961793679185406569603087713848658818990582926259
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 714966653 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 714966653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 8 failures:
  • Test sram_ctrl_readback_err has 8 failures.

    • 1.sram_ctrl_readback_err.9301177482068198565163092783705693232385355770806673698287349933110275888070
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 698914637 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x63) != exp (0xa)
        UVM_INFO @ 698914637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.16537183568826637865593276453326747949311217914542194119223830244650575582793
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1419646415 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x27) != exp (0x1b)
        UVM_INFO @ 1419646415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.10517904642028493783608772269246069415244405026401305076063572835024117820561
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10174682 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10174682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.87540485734323007747178925188565193175486037179646202751468439748772318136092
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8066283 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8066283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.74857088775746261637191139276566848607982119004492919164334895747714183832228
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  17061537 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  17061537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---