SRAM_CTRL/RET Simulation Results

Friday October 10 2025 17:09:47 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.866m	4.516ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	69.475us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.030s	26.974us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	150.906us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	74.573us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.240s	105.822us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.030s	26.974us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	74.573us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.190s	5.919ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.840s	208.726us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	16.618m	103.371ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.107m	17.923ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.639m	30.183ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.582m	5.598ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.710s	3.486ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.939m	14.321ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.616m	2.689ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.233m	98.276ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.887m	504.283us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.405m	154.629us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.724m	295.401us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.581m	39.667ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.180s	64.729us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.100h	239.625ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	94.159us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.880s	168.406us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.880s	168.406us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	69.475us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	26.974us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	74.573us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	113.756us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	69.475us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	26.974us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	74.573us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	113.756us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.880s	1.075ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
		sram_ctrl_tl_intg_err	3.070s	230.467us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.070s	230.467us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.581m	39.667ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.581m	39.667ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.030s	26.974us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.939m	14.321ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.939m	14.321ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.939m	14.321ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.710s	3.486ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.630s	72.517us	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.880s	1.075ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.560s	65.083us	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.866m	4.516ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.866m	4.516ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.939m	14.321ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.710s	3.486ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.866m	4.516ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.990s	3.298us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.269m	18.521ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 12 failures:
- Test sram_ctrl_readback_err has 12 failures.
  - 2.sram_ctrl_readback_err.55700270375242378438241407608062082593404355650038695806062532451078012091069
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  31961215 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x1f)
  UVM_INFO @  31961215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.sram_ctrl_readback_err.10591649347278806876554821573309528651957110886170418803982903061450471671740
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 110435328 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x14) != exp (0x62)
  UVM_INFO @ 110435328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
Offending 'reqfifo_rvalid' has 7 failures:
- Test sram_ctrl_mubi_enc_err has 7 failures.
  - 0.sram_ctrl_mubi_enc_err.10115878223080614213844847137616226206028699840062046168315807653634405601889
    Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 107373594 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 107373594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.sram_ctrl_mubi_enc_err.26864975178536074986836775561064648760132490176183975168849420423347505877594
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 273372053 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 273372053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
- Test sram_ctrl_sec_cm has 4 failures.
  - 0.sram_ctrl_sec_cm.64775770817993956515320265170547387650304549634121838248802843386195057321500
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3297830 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3297830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.77847154668722620459640100946931995370898238487549331944228622043191497295374
    Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   7857233 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   7857233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.59778445787419649700493368440081144452715839518787201242674068347271244277323
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127119441 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 127119441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.8643888947036610978891673841250001395260710561458963845044619452955416657706
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1938796 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1938796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4016) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

11.sram_ctrl_mubi_enc_err.107361306951200514961904535653049685681209504349167289101776201310397277206994
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @  27966257 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4016) { a_addr: 'ha9ae374  a_data: 'h42  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4e  a_opcode: 'h1  a_user: 'h276d4  d_param: 'h0  d_source: 'h4e  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  27966257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.31282497419810432835243015417761554601502951616327753226430754709479910706429
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24473947 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  24473947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```