AES/MASKED Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	65.577us	1	1	100.00
V1	smoke	aes_smoke	9.000s	1.284ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	52.874us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	126.851us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1.086ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	493.789us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	73.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	126.851us	20	20	100.00
		aes_csr_aliasing	4.000s	493.789us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	1.284ms	50	50	100.00
		aes_config_error	8.000s	995.607us	50	50	100.00
		aes_stress	11.000s	1.779ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	1.284ms	50	50	100.00
		aes_config_error	8.000s	995.607us	50	50	100.00
		aes_stress	11.000s	1.779ms	50	50	100.00
V2	back2back	aes_stress	11.000s	1.779ms	50	50	100.00
		aes_b2b	25.000s	377.088us	50	50	100.00
V2	backpressure	aes_stress	11.000s	1.779ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	1.284ms	50	50	100.00
		aes_config_error	8.000s	995.607us	50	50	100.00
		aes_stress	11.000s	1.779ms	50	50	100.00
		aes_alert_reset	23.000s	2.036ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	989.379us	50	50	100.00
		aes_config_error	8.000s	995.607us	50	50	100.00
		aes_alert_reset	23.000s	2.036ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	965.778us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	692.657us	1	1	100.00
V2	reset_recovery	aes_alert_reset	23.000s	2.036ms	50	50	100.00
V2	stress	aes_stress	11.000s	1.779ms	50	50	100.00
V2	sideload	aes_stress	11.000s	1.779ms	50	50	100.00
		aes_sideload	8.000s	471.798us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	339.018us	50	50	100.00
V2	stress_all	aes_stress_all	53.000s	3.997ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	214.901us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	489.513us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	489.513us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	52.874us	5	5	100.00
		aes_csr_rw	3.000s	126.851us	20	20	100.00
		aes_csr_aliasing	4.000s	493.789us	5	5	100.00
		aes_same_csr_outstanding	3.000s	432.533us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	52.874us	5	5	100.00
		aes_csr_rw	3.000s	126.851us	20	20	100.00
		aes_csr_aliasing	4.000s	493.789us	5	5	100.00
		aes_same_csr_outstanding	3.000s	432.533us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	22.000s	1.240ms	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	275.118us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	2.277ms	5	5	100.00
		aes_tl_intg_err	3.000s	324.223us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	324.223us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	23.000s	2.036ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	1.284ms	50	50	100.00
		aes_stress	11.000s	1.779ms	50	50	100.00
		aes_alert_reset	23.000s	2.036ms	50	50	100.00
		aes_core_fi	4.750m	10.009ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	642.195us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	304.056us	50	50	100.00
		aes_stress	11.000s	1.779ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	1.779ms	50	50	100.00
		aes_sideload	8.000s	471.798us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	304.056us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	304.056us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	304.056us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	304.056us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	304.056us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	1.779ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	1.779ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	530.915us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	530.915us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	53.000s	10.012ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	530.915us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	23.000s	2.036ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_ctr_fi	3.000s	64.199us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	530.915us	47	50	94.00
		aes_control_fi	57.000s	10.007ms	283	300	94.33
		aes_cipher_fi	53.000s	10.012ms	339	350	96.86
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.000s	19.613ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.59	96.41	99.42	95.35	97.99	97.78	98.36	97.79

Failure Buckets

Job timed out after * minutes has 10 failures:
- Test aes_cipher_fi has 2 failures.
  - 22.aes_cipher_fi.63532415713956186607364016873356096816871526618010229160180785010558220387540
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 300.aes_cipher_fi.1782683193600497564649050625144726335702669791571334885200446098721354969585
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/300.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 8 failures.
  - 27.aes_control_fi.51090812461916367782573318275502148341647283773719636941554193657260499509865
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 110.aes_control_fi.63451666442903434022483329149731035381169333271717386682329108396704845937254
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/110.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 14.aes_control_fi.105411153510189266883169585066357778945246188663130068622847143145528331851850
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006366033 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006366033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.aes_control_fi.109910826056590029254221985041386914506464167738369474562668507554069731679555
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009528475 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009528475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 23.aes_cipher_fi.54627263109579528481766610032473822024937478068684337885914295832764666889882
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007537890 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007537890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 115.aes_cipher_fi.6374507437327298755083504239312240491657868542703352914305336333619691635568
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/115.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008779942 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008779942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.57822946001210192609176043806084459377064968966613924766713271247554787830459
Line 468, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 601177352 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 601177352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.52901172102211429879044196884696486518693694613326586001209307719139673551651
Line 565, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 639487048 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 639487048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 3 failures:

Test aes_fi has 3 failures.

1.aes_fi.112478532207863753852290931029816266057477749645235504071930041200938195059486
Line 10885, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_fi/latest/run.log

  UVM_FATAL @ 143859736 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 143859736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aes_fi.14485095530836246770133459002015661556993203969006967350656158007899452574705
Line 15437, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/22.aes_fi/latest/run.log

  UVM_FATAL @  70496210 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  70496210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.39661636868611379400287883714533336039914194898267199536373906257335241080453
    Line 1197, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19612881847 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 19612881847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.64513619714882592914053793209421831460696410823930846779649253476715360023616
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  56545398 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  56545398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.40281548996862991005677923665774542913538135499955404244181034484985072461750
    Line 638, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 629685699 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 629685699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.112771352097115441097510017505855121080688523409698056487997085784237824403710
    Line 274, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2413892615 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2413892615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 54.aes_core_fi.21445158543911209431266828385624672827182861230942358603057407427003220326063
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003958788 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003958788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 67.aes_core_fi.33495465153520212617156524872909124617034750571282073959951983034415503731506
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024298407 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024298407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.6117358727981090642251503489525828856989055542207520972465691210690047481582
    Line 256, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 538483740 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 538483740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.98744046326423529760040372260778323226312682629143392304218579658073570619534
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009476223 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x8c67ea84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10009476223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```