AES/UNMASKED Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	87.794us	1	1	100.00
V1	smoke	aes_smoke	4.000s	390.745us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	77.609us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	184.489us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	6.641ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	200.307us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	121.203us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	184.489us	20	20	100.00
		aes_csr_aliasing	4.000s	200.307us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	390.745us	50	50	100.00
		aes_config_error	8.000s	435.791us	50	50	100.00
		aes_stress	3.000s	69.303us	50	50	100.00
V2	key_length	aes_smoke	4.000s	390.745us	50	50	100.00
		aes_config_error	8.000s	435.791us	50	50	100.00
		aes_stress	3.000s	69.303us	50	50	100.00
V2	back2back	aes_stress	3.000s	69.303us	50	50	100.00
		aes_b2b	6.000s	634.551us	50	50	100.00
V2	backpressure	aes_stress	3.000s	69.303us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	390.745us	50	50	100.00
		aes_config_error	8.000s	435.791us	50	50	100.00
		aes_stress	3.000s	69.303us	50	50	100.00
		aes_alert_reset	4.000s	285.993us	49	50	98.00
V2	failure_test	aes_man_cfg_err	3.000s	91.008us	50	50	100.00
		aes_config_error	8.000s	435.791us	50	50	100.00
		aes_alert_reset	4.000s	285.993us	49	50	98.00
V2	trigger_clear_test	aes_clear	5.000s	903.600us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	294.273us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	285.993us	49	50	98.00
V2	stress	aes_stress	3.000s	69.303us	50	50	100.00
V2	sideload	aes_stress	3.000s	69.303us	50	50	100.00
		aes_sideload	3.000s	144.874us	50	50	100.00
V2	deinitialization	aes_deinit	3.000s	109.453us	50	50	100.00
V2	stress_all	aes_stress_all	19.000s	1.658ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	85.705us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	86.057us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	86.057us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	77.609us	5	5	100.00
		aes_csr_rw	5.000s	184.489us	20	20	100.00
		aes_csr_aliasing	4.000s	200.307us	5	5	100.00
		aes_same_csr_outstanding	3.000s	126.175us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	77.609us	5	5	100.00
		aes_csr_rw	5.000s	184.489us	20	20	100.00
		aes_csr_aliasing	4.000s	200.307us	5	5	100.00
		aes_same_csr_outstanding	3.000s	126.175us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	4.000s	209.755us	50	50	100.00
V2S	fault_inject	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	114.205us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	2.330ms	5	5	100.00
		aes_tl_intg_err	7.000s	558.349us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	558.349us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	285.993us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	390.745us	50	50	100.00
		aes_stress	3.000s	69.303us	50	50	100.00
		aes_alert_reset	4.000s	285.993us	49	50	98.00
		aes_core_fi	35.000s	10.002ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	124.446us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	64.181us	50	50	100.00
		aes_stress	3.000s	69.303us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	69.303us	50	50	100.00
		aes_sideload	3.000s	144.874us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	64.181us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	64.181us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	64.181us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	64.181us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	64.181us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	69.303us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	69.303us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	32.617m	200.000ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	32.617m	200.000ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	29.000s	10.005ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	32.617m	200.000ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	285.993us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_ctr_fi	3.000s	60.528us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	32.617m	200.000ms	49	50	98.00
		aes_control_fi	35.000s	10.004ms	288	300	96.00
		aes_cipher_fi	29.000s	10.005ms	328	350	93.71
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.000s	1.371ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.33	97.77	94.97	98.80	93.44	98.07	93.33	98.08	98.19

Failure Buckets

Job timed out after * minutes has 19 failures:
- Test aes_cipher_fi has 14 failures.
  - 21.aes_cipher_fi.10115260227561148597071438695170923529986995163897367930037467004993157140208
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 39.aes_cipher_fi.45935782514977548120805308752735865527606267875885799378835621043426499465944
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_control_fi has 5 failures.
  - 27.aes_control_fi.100408138525252062642398935336679954763897704010006419788119259806838771524155
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 46.aes_control_fi.65146658816682342937253451438440549010593972285526188017825112839609959581537
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 48.aes_cipher_fi.24615461986405962604628553712628933169641634785578524502906824436122175608117
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/48.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011230727 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011230727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 104.aes_cipher_fi.113611430521453748566773141799899385564905208356347224129863604479329887000744
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011895853 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011895853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.86316731802928419392123582513521249852597214367204219067804015819072097247977
Line 214, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  25562370 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  25562370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.88707447265323122183383176307055123924224455368890736842376786914954433906357
Line 887, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 876578417 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 876578417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 36.aes_control_fi.905542706777569102592499420377506595713485394751138270781770605612019825728
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008989283 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008989283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 102.aes_control_fi.65417949551073840634880021244058913184925714345378045640977871128522771086277
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/102.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006788796 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006788796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 2.aes_core_fi.4164041916853730628179995103424699948258417247669554048064220409911045165525
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015820838 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015820838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.aes_core_fi.81396511463132243532104936956105893965126744785803632241923768715807157697025
    Line 132, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015418259 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015418259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.20680194234649129657857164568185099468062001717792418761384792443426902574927
    Line 656, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2081414585 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2081414585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.101780178600897095919580681473027253948783296705529751405652188653963119176518
    Line 202, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 272678146 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 272678146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.111774222140867142324383829218985045194230234130408171517543869878921919072012
    Line 158, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1217106666 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1217106666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_fi has 1 failures.
  - 24.aes_fi.46376866357883496708856647986163158085908487619941414283735250835562391101570
    Line 22999373, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

42.aes_alert_reset.68880233710764327174344630866104581519042723645145280059873115607109655432001
Line 1132, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/42.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 14599691 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 14588197 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 14599691 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 14588197 PS)
  UVM_ERROR @  14599691 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut