CSRNG Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	226.830us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	15.402us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	68.787us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	25.000s	2.536ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	84.619us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	291.226us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	68.787us	20	20	100.00
		csrng_csr_aliasing	5.000s	84.619us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	982.402us	196	200	98.00
V2	alerts	csrng_alert	1.033m	5.488ms	500	500	100.00
V2	err	csrng_err	14.000s	100.423us	497	500	99.40
V2	cmds	csrng_cmds	7.217m	34.304ms	50	50	100.00
V2	life cycle	csrng_cmds	7.217m	34.304ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.183m	94.477ms	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	77.475us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	195.389us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	314.467us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	314.467us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	15.402us	5	5	100.00
		csrng_csr_rw	3.000s	68.787us	20	20	100.00
		csrng_csr_aliasing	5.000s	84.619us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	283.591us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	15.402us	5	5	100.00
		csrng_csr_rw	3.000s	68.787us	20	20	100.00
		csrng_csr_aliasing	5.000s	84.619us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	283.591us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	4.000s	128.881us	5	5	100.00
		csrng_tl_intg_err	12.000s	1.348ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	89.031us	50	50	100.00
		csrng_csr_rw	3.000s	68.787us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.033m	5.488ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.183m	94.477ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.033m	5.488ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.183m	94.477ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.033m	5.488ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	1.348ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
		csrng_sec_cm	4.000s	128.881us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	982.402us	196	200	98.00
		csrng_err	14.000s	100.423us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.767m	31.280ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1620	1630	99.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.57	98.50	96.30	99.91	97.14	91.96	100.00	95.25	90.36

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 7 failures:
  • Test csrng_intr has 4 failures.

    • 11.csrng_intr.67395059478715608068853875897992146186030834473098194222298182326807682847195
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 273551542 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 273551542 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 273551542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 68.csrng_intr.44561132357963210551374261199007937707339632705203181069304894893034243765103
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/68.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 105883932 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 105883932 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 105883932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

  • Test csrng_err has 3 failures.

    • 38.csrng_err.73556580800684095359053890682113611037572394039680846952020299568828947733654
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/38.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 2411225 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   2411225 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2411225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 293.csrng_err.107905623851802452759022943517538709963981672473867768155496751174551908007079
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/293.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 51112171 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  51112171 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  51112171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 31.csrng_stress_all.110385836898783265245466982045336442186402302658520279649240136534933507080505
      Line 162, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/31.csrng_stress_all/latest/run.log

        UVM_ERROR @  98903492 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  98903492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 33.csrng_stress_all.108886410358884302058102172497727654203795572633496310523742845190328079309542
      Line 160, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/33.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2639091733 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2639091733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.