DMA Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	311.050us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	718.709us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.170ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	113.208us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	103.601us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	8.727ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	448.748us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	26.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	103.601us	20	20	100.00
		dma_csr_aliasing	9.000s	448.748us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.283m	6.224ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.150m	35.143ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	9.250m	188.369ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	9.250m	188.369ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	7.150m	35.143ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	23.683m	428.157ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	9.250m	188.369ms	3	3	100.00
V2	dma_abort	dma_abort	13.000s	3.215ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.700m	20.400ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	11.389us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	22.084us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	161.783us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	161.783us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	113.208us	5	5	100.00
		dma_csr_rw	2.000s	103.601us	20	20	100.00
		dma_csr_aliasing	9.000s	448.748us	5	5	100.00
		dma_same_csr_outstanding	3.000s	297.209us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	113.208us	5	5	100.00
		dma_csr_rw	2.000s	103.601us	20	20	100.00
		dma_csr_aliasing	9.000s	448.748us	5	5	100.00
		dma_same_csr_outstanding	3.000s	297.209us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	31.000s	91.316us	5	5	100.00
		dma_generic_stress	23.683m	428.157ms	5	5	100.00
		dma_handshake_stress	9.250m	188.369ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	330.021us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	511.806us	20	20	100.00
		dma_sec_cm	2.000s	23.658us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.717m	45.880ms	25	25	100.00
		dma_longer_transfer	12.000s	367.734us	5	5	100.00
		dma_stress_all_with_rand_reset	17.000s	973.652us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.53	97.38	95.83	96.89	95.99	77.37	92.96	95.97	78.73

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.90857756405478517178345996707763852757236702990065934276503218413782493803587
      Line 134, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  973651719ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  973651719ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---