EDN Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.250s 24.299us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.970s 69.701us 5 5 100.00
V1 csr_rw edn_csr_rw 1.030s 29.728us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.780s 661.959us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.390s 20.316us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.700s 63.315us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.030s 29.728us 20 20 100.00
edn_csr_aliasing 1.390s 20.316us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.668m 9.111ms 300 300 100.00
V2 csrng_commands edn_genbits 1.668m 9.111ms 300 300 100.00
V2 genbits edn_genbits 1.668m 9.111ms 300 300 100.00
V2 interrupts edn_intr 1.650s 22.376us 50 50 100.00
V2 alerts edn_alert 1.590s 81.436us 200 200 100.00
V2 errs edn_err 1.560s 25.574us 100 100 100.00
V2 disable edn_disable 1.360s 14.700us 50 50 100.00
edn_disable_auto_req_mode 1.550s 26.854us 50 50 100.00
V2 stress_all edn_stress_all 4.800s 272.676us 50 50 100.00
V2 intr_test edn_intr_test 1.100s 17.977us 50 50 100.00
V2 alert_test edn_alert_test 2.970s 219.867us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.210s 439.093us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.210s 439.093us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.970s 69.701us 5 5 100.00
edn_csr_rw 1.030s 29.728us 20 20 100.00
edn_csr_aliasing 1.390s 20.316us 5 5 100.00
edn_same_csr_outstanding 1.510s 66.010us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.970s 69.701us 5 5 100.00
edn_csr_rw 1.030s 29.728us 20 20 100.00
edn_csr_aliasing 1.390s 20.316us 5 5 100.00
edn_same_csr_outstanding 1.510s 66.010us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.300s 1.244ms 5 5 100.00
edn_tl_intg_err 2.890s 197.385us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.290s 30.216us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.590s 81.436us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.300s 1.244ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.300s 1.244ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.300s 1.244ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.300s 1.244ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.590s 81.436us 200 200 100.00
edn_sec_cm 7.300s 1.244ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.590s 81.436us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.890s 197.385us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.940m 39.117ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1107 1130 97.96

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.56 98.87 94.23 96.97 91.86 96.33 97.56 93.13

Failure Buckets