HMAC Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.850s	544.802us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.320s	157.753us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.260s	16.964us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.660s	4.181ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.830s	3.460ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.715m	579.225ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.260s	16.964us	20	20	100.00
		hmac_csr_aliasing	7.830s	3.460ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.212m	6.196ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.683m	9.530ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.165m	6.283ms	30	30	100.00
		hmac_test_sha384_vectors	9.593m	22.982ms	75	75	100.00
		hmac_test_sha512_vectors	8.470m	37.632ms	75	75	100.00
		hmac_test_hmac256_vectors	13.970s	1.282ms	50	50	100.00
		hmac_test_hmac384_vectors	15.870s	405.829us	60	60	100.00
		hmac_test_hmac512_vectors	19.570s	454.947us	75	75	100.00
V2	burst_wr	hmac_burst_wr	36.530s	7.805ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.159m	7.839ms	10	10	100.00
V2	error	hmac_error	1.755m	2.826ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.090m	119.763ms	10	10	100.00
V2	save_and_restore	hmac_smoke	11.850s	544.802us	10	10	100.00
		hmac_long_msg	1.212m	6.196ms	10	10	100.00
		hmac_back_pressure	1.683m	9.530ms	25	25	100.00
		hmac_datapath_stress	22.159m	7.839ms	10	10	100.00
		hmac_burst_wr	36.530s	7.805ms	50	50	100.00
		hmac_stress_all	30.334m	23.349ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.850s	544.802us	10	10	100.00
		hmac_long_msg	1.212m	6.196ms	10	10	100.00
		hmac_back_pressure	1.683m	9.530ms	25	25	100.00
		hmac_datapath_stress	22.159m	7.839ms	10	10	100.00
		hmac_wipe_secret	2.090m	119.763ms	10	10	100.00
		hmac_test_sha256_vectors	4.165m	6.283ms	30	30	100.00
		hmac_test_sha384_vectors	9.593m	22.982ms	75	75	100.00
		hmac_test_sha512_vectors	8.470m	37.632ms	75	75	100.00
		hmac_test_hmac256_vectors	13.970s	1.282ms	50	50	100.00
		hmac_test_hmac384_vectors	15.870s	405.829us	60	60	100.00
		hmac_test_hmac512_vectors	19.570s	454.947us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.850s	544.802us	10	10	100.00
		hmac_long_msg	1.212m	6.196ms	10	10	100.00
		hmac_back_pressure	1.683m	9.530ms	25	25	100.00
		hmac_datapath_stress	22.159m	7.839ms	10	10	100.00
		hmac_burst_wr	36.530s	7.805ms	50	50	100.00
		hmac_error	1.755m	2.826ms	10	10	100.00
		hmac_wipe_secret	2.090m	119.763ms	10	10	100.00
		hmac_test_sha256_vectors	4.165m	6.283ms	30	30	100.00
		hmac_test_sha384_vectors	9.593m	22.982ms	75	75	100.00
		hmac_test_sha512_vectors	8.470m	37.632ms	75	75	100.00
		hmac_test_hmac256_vectors	13.970s	1.282ms	50	50	100.00
		hmac_test_hmac384_vectors	15.870s	405.829us	60	60	100.00
		hmac_test_hmac512_vectors	19.570s	454.947us	75	75	100.00
		hmac_stress_all	30.334m	23.349ms	50	50	100.00
V2	stress_all	hmac_stress_all	30.334m	23.349ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	48.564us	50	50	100.00
V2	intr_test	hmac_intr_test	0.940s	38.998us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.760s	68.015us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.760s	68.015us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.320s	157.753us	5	5	100.00
		hmac_csr_rw	1.260s	16.964us	20	20	100.00
		hmac_csr_aliasing	7.830s	3.460ms	5	5	100.00
		hmac_same_csr_outstanding	2.780s	484.720us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.320s	157.753us	5	5	100.00
		hmac_csr_rw	1.260s	16.964us	20	20	100.00
		hmac_csr_aliasing	7.830s	3.460ms	5	5	100.00
		hmac_same_csr_outstanding	2.780s	484.720us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.400s	467.712us	5	5	100.00
		hmac_tl_intg_err	4.910s	1.077ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.910s	1.077ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.850s	544.802us	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.290s	1.003ms	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.107m	50.983ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.390s	41.413us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.19	99.95	96.91	100.00	100.00	99.83	97.61	100.00