I2C Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.437m	3.950ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	37.780s	4.788ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.080s	25.380us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.420s	764.124us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.060s	479.026us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.210s	120.910us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.850s	192.493us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.420s	764.124us	20	20	100.00
		i2c_csr_aliasing	2.210s	120.910us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	5.170s	296.371us	1	50	2.00
V2	host_stress_all	i2c_host_stress_all	57.345m	145.440ms	12	50	24.00
V2	host_maxperf	i2c_host_perf	31.428m	50.143ms	50	50	100.00
V2	host_override	i2c_host_override	1.060s	29.895us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.153m	33.467ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.503m	9.496ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.620s	530.805us	50	50	100.00
		i2c_host_fifo_fmt_empty	20.750s	1.629ms	50	50	100.00
		i2c_host_fifo_reset_rx	10.440s	1.568ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.899m	14.642ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	30.950s	819.634us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.010s	299.146us	18	50	36.00
V2	target_glitch	i2c_target_glitch	2.210s	2.172ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	23.789m	69.677ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	8.740s	896.685us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.076m	6.945ms	50	50	100.00
		i2c_target_intr_smoke	9.040s	4.412ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.550s	1.904ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.650s	318.821us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	23.933m	66.847ms	50	50	100.00
		i2c_target_stress_rd	1.076m	6.945ms	50	50	100.00
		i2c_target_intr_stress_wr	5.947m	23.075ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	8.690s	20.600ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.286m	4.244ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	7.560s	4.879ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	30.290s	10.285ms	27	50	54.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.060s	2.373ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.900s	453.179us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	31.428m	50.143ms	50	50	100.00
		i2c_host_perf_precise	5.057m	5.821ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	30.950s	819.634us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	30.690s	2.543ms	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.060s	1.086ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.550s	504.636us	50	50	100.00
		i2c_target_nack_txstretch	2.300s	212.980us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	24.600s	785.545us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.500s	518.769us	50	50	100.00
V2	alert_test	i2c_alert_test	0.980s	29.941us	50	50	100.00
V2	intr_test	i2c_intr_test	1.040s	30.243us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.180s	516.858us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.180s	516.858us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.080s	25.380us	5	5	100.00
		i2c_csr_rw	2.420s	764.124us	20	20	100.00
		i2c_csr_aliasing	2.210s	120.910us	5	5	100.00
		i2c_same_csr_outstanding	1.510s	129.068us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.080s	25.380us	5	5	100.00
		i2c_csr_rw	2.420s	764.124us	20	20	100.00
		i2c_csr_aliasing	2.210s	120.910us	5	5	100.00
		i2c_same_csr_outstanding	1.510s	129.068us	20	20	100.00
V2		TOTAL			1626	1792	90.74
V2S	tl_intg_err	i2c_tl_intg_err	2.690s	120.176us	20	20	100.00
		i2c_sec_cm	1.360s	77.025us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.690s	120.176us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	43.370s	1.769ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.550s	504.417us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	32.350s	4.408ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1806	2042	88.44

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.98	97.25	89.18	74.17	47.62	93.83	96.41	89.43

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 90 failures:

Test i2c_host_error_intr has 49 failures.

0.i2c_host_error_intr.11883708853924639173912714232405844475150529762700756196280456864827312412165
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  10160493 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  10160493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.66817420780526928774977709627417358408131986306203102909910059391737614144953
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  10746195 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  10746195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 47 more failures.

Test i2c_host_stress_all has 27 failures.

1.i2c_host_stress_all.69299333403789359028457232785366256177691974586037825264035583246393686219798
Line 110, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 7668955831 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 7668955831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all.37350662648747200776329140490156180654656467932753123329794012002216057965884
Line 145, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 32992186360 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 32992186360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

2.i2c_target_stress_all_with_rand_reset.89331285580157534284730572100064863871331102366417744200859796262322481676189
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 277907315 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 277907315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_stress_all_with_rand_reset.92777963775623568710089836881675991583352976021999372256349051367149960423205
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  57205359 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  57205359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_host_mode_toggle has 11 failures.

8.i2c_host_mode_toggle.21036522354946747911529397143339394996684684199269050501564848932458629844846
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 113047929 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 113047929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_host_mode_toggle.66341967499250548865988949631010627108351582728331347221432143537513948167301
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  16791909 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  16791909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
- Test i2c_target_unexp_stop has 28 failures.
  - 0.i2c_target_unexp_stop.85955222048399195000489584002837895123255231804282435484658765119274571127752
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 183147913 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 119 [0x77])
  UVM_INFO @ 183147913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.72411486414206077360390443590266753330934522173288679618171808824056370787527
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 339662491 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 179 [0xb3])
  UVM_INFO @ 339662491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
- Test i2c_target_hrst has 23 failures.
  - 2.i2c_target_hrst.103058945317573167894066050807068954002565079954132526331407138001196672160489
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10201305222 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10201305222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_hrst.87600424148055864379080832817727753644461283305641701844141222581355672664421
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10052500321 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10052500321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 1.i2c_target_unexp_stop.24130532055777872292945192314223782219479071759855402277648593908457021106996
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 206999518 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 206999518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.60881745301783959075769429021856252739805170997099940713187548348568645762442
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  99920085 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  99920085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.101426298164525123754196309462078082317408917400296772658899814644683489309752
Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1306871900 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1306871900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.78838508914484088641062905578432828690330977333720590519997891214224040091339
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1096211497 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1096211497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.55641770741341554133732022791786791618109817794834324973829678219576489437802
Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 457758112 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 457758112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.64724900814805884390601348036304495603865872835192665880371549267512156307556
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1810042717 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1810042717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 14 failures:

Test i2c_host_stress_all has 8 failures.

0.i2c_host_stress_all.110694564618211274674541869548771720126466733518084450471527611921292060581501
Line 122, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26101222632 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @14353689

19.i2c_host_stress_all.84716726742408436897806922601586512281367084299398460613814390938855970106147
Line 142, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18460240800 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1897685

... and 6 more failures.

Test i2c_host_mode_toggle has 6 failures.

16.i2c_host_mode_toggle.92567528336431156729604740259334628368840621935728118968972898344750714471552
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  77870627 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @42574

19.i2c_host_mode_toggle.85627443385871697019815044806405133460584814863438329568754936047334607688214
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 335585241 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @12594

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 3.i2c_target_nack_txstretch.86524325735168121614596738674540203713945533163100796148435835584772528484892
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 2542055206 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 2542055206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_nack_txstretch.87370483043616654250055669426404229263258598960376338428621623968157345434634
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 194946816 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 194946816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:

Test i2c_host_mode_toggle has 12 failures.

4.i2c_host_mode_toggle.17508373886621301371354694592202167854722535098991459053852683018060031742670
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 150622174 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

5.i2c_host_mode_toggle.99032789255283456847386357878668333998707664680726252979365137124098850387715
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 186427763 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

4.i2c_target_unexp_stop.83143640790916067024438940002876066834170340180525052001741248361718764004540
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 874094136 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 874094136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_target_unexp_stop.18488069175299038848534656394754999236449316576700245364667432140565559691545
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 590249234 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 590249234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 21.i2c_target_stretch.36506427282387135299686810016739719685381689034960473741216873670818835302566
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10022677699 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10022677699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.i2c_target_stretch.89496336751159530431547686270440696199258047815621964325466521527697770945561
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001442091 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001442091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.21659088682907207377468738405394464657589285964216517237054714101174080230265
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 397561323 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 397561323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.2603856255867359732457515484819584741990741403126695258401649642758025574508
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2172263946 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2172263946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.44262864057509787295248992711469312701961696928223758927273281426962346679166
    Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 735666062 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 735666062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_stress_all_with_rand_reset.18510641177553434431322438053829144751002401231567938338192963141620164789509
    Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 978252646 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 978252646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

Test i2c_host_mode_toggle has 2 failures.

1.i2c_host_mode_toggle.3585498705656901273448528723158531299961605688368137457543986016169560642042
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 248135658 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x87309b14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 248135658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_host_mode_toggle.32593008921769076758795748344508860318851254777396822712799682588384237263357
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @  56572597 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xa44ab94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  56572597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 1 failures.
  - 11.i2c_target_stress_all.22904909536127906583148697735380748176642843581991223056932480746172328371286
    Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 69677224117 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 69677224117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_intr_stress_wr has 1 failures.
  - 26.i2c_target_intr_stress_wr.51654823333348850518364377349732249527276997581118945878336522251803435247708
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 30892640660 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 30892640660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 12.i2c_host_stress_all.92001299161239752100469502153255014047988090209096448911871672057610377605030
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 15.i2c_host_stress_all.73720283106214989395752563950028024834693658510220983747230030161954819049030
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 4.i2c_host_stress_all.104385966063823845688404759797124198471173485862943461286132149512464410000406
    Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 6.i2c_host_mode_toggle.63480469245780422693868178728798191310885108540322105253176021770146123566239
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 36.i2c_target_tx_stretch_ctrl.95530994913893763402773948741327913201341116507322615296659171691581980518495
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```