KEYMGR Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.750s	4.275ms	50	50	100.00
V1	random	keymgr_random	29.120s	4.859ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.310s	20.344us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.400s	88.880us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.510s	2.689ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.600s	465.436us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.000s	36.367us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.400s	88.880us	20	20	100.00
		keymgr_csr_aliasing	12.600s	465.436us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.131m	2.395ms	50	50	100.00
V2	sideload	keymgr_sideload	26.660s	4.251ms	50	50	100.00
		keymgr_sideload_kmac	18.760s	1.872ms	50	50	100.00
		keymgr_sideload_aes	31.440s	3.496ms	50	50	100.00
		keymgr_sideload_otbn	35.000s	3.655ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.050s	2.986ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	28.010s	2.779ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.450s	1.429ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	47.930s	6.519ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	35.970s	2.794ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.530s	435.481us	50	50	100.00
V2	stress_all	keymgr_stress_all	3.494m	15.617ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.280s	57.391us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.430s	309.716us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.090s	161.253us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.090s	161.253us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.310s	20.344us	5	5	100.00
		keymgr_csr_rw	1.400s	88.880us	20	20	100.00
		keymgr_csr_aliasing	12.600s	465.436us	5	5	100.00
		keymgr_same_csr_outstanding	3.120s	376.725us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.310s	20.344us	5	5	100.00
		keymgr_csr_rw	1.400s	88.880us	20	20	100.00
		keymgr_csr_aliasing	12.600s	465.436us	5	5	100.00
		keymgr_same_csr_outstanding	3.120s	376.725us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
		keymgr_tl_intg_err	7.130s	536.599us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.120s	453.592us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.120s	453.592us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.120s	453.592us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.120s	453.592us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.430s	2.676ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.130s	536.599us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.120s	453.592us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.131m	2.395ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	29.120s	4.859ms	50	50	100.00
		keymgr_csr_rw	1.400s	88.880us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	29.120s	4.859ms	50	50	100.00
		keymgr_csr_rw	1.400s	88.880us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	29.120s	4.859ms	50	50	100.00
		keymgr_csr_rw	1.400s	88.880us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	28.010s	2.779ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	35.970s	2.794ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	35.970s	2.794ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	29.120s	4.859ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	15.960s	547.711us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	8.790s	1.014ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	28.010s	2.779ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	8.790s	1.014ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	8.790s	1.014ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	8.790s	1.014ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.340s	1.233ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	8.790s	1.014ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.210s	3.464ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1080	1110	97.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.13	98.30	98.29	100.00	99.01	97.71	91.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test keymgr_stress_all_with_rand_reset has 25 failures.
  - 0.keymgr_stress_all_with_rand_reset.20204353449451489845205499877715796593398787126907688845087531942179202415210
    Line 395, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 247013263 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 247013263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.79096890242127560750445737343958794108162165837002894529318649083298900558606
    Line 2099, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 433248330 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 433248330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 23 more failures.

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Sealing Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

2.keymgr_lc_disable.36734192676049250406647275065539387286130350739470027514219399099150288756419
Line 345, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  35020512 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (11817286390633513095383623698674214550992966037956610501485163578447388035632127621113318040407280284599696997161819248589431742691879004673681389841301050 [0xe1a1b1522e111d1fe6d54d3f664c9a4a771d7c9d0c3546e2f1502727785d1f5f8b88617016186f1b912f2552dcaa6707f8eb48f9fdc72e348f811b3365383e3a] vs 11817286390633513095383623698674214550992966037956610501485163578447388035632127621113318040407280284599696997161819248589431742691879004673681389841301050 [0xe1a1b1522e111d1fe6d54d3f664c9a4a771d7c9d0c3546e2f1502727785d1f5f8b88617016186f1b912f2552dcaa6707f8eb48f9fdc72e348f811b3365383e3a]) KMAC key at state StOwnerKey for Sealing Kmac
  UVM_INFO @  35020512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 6.keymgr_stress_all_with_rand_reset.49285015353753288436797914952732215167827671994462844932809930194622321080939
    Line 1123, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 715336618 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 715336618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 12.keymgr_hwsw_invalid_input.7745803126291755566208570277940929130355963054141676316176365676884679868160
    Line 112, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  10491355 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  10491355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 15.keymgr_stress_all.83224760717951794392030671010431622698945672845609498337721675206318460063666
    Line 2016, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2789289343 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @ 2789289343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 16.keymgr_stress_all_with_rand_reset.23991087003061661604071496588666733797923896652307594813776693330717761928255
    Line 313, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 910454930 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
  UVM_INFO @ 910454930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```