KEYMGR_DPE Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.078m	96.445ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.850s	58.930us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.300s	41.852us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	13.970s	1.146ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.690s	86.443us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.080s	93.282us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.300s	41.852us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.690s	86.443us	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	1.250s	17.322us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.340s	19.285us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.500s	168.190us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.500s	168.190us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.850s	58.930us	5	5	100.00
		keymgr_dpe_csr_rw	1.300s	41.852us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.690s	86.443us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.270s	77.681us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.850s	58.930us	5	5	100.00
		keymgr_dpe_csr_rw	1.300s	41.852us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.690s	86.443us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.270s	77.681us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	15.010s	963.488us	5	5	100.00
		keymgr_dpe_tl_intg_err	10.760s	509.479us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.200s	306.520us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.200s	306.520us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.200s	306.520us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.200s	306.520us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.310s	442.584us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	15.010s	963.488us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	15.010s	963.488us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			308	310	99.35

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.59	97.62	90.26	63.15	75.68	94.61	97.62	17.18

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
  • Test keymgr_dpe_smoke has 2 failures.

    • 4.keymgr_dpe_smoke.11239924575983327288515551482532677128366575475387605027691023046593814493128
      Line 1401, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/4.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 774389606 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 774389606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 36.keymgr_dpe_smoke.7545860711756448593878293212044568289355737198988376728406421143285337945103
      Line 133, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/36.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @   5698529 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @   5698529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---