KMAC/MASKED Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.230m	3.042ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.320s	74.911us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.440s	33.560us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.250s	1.120ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.790s	493.351us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.330s	34.152us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.440s	33.560us	20	20	100.00
		kmac_csr_aliasing	7.790s	493.351us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.040s	12.631us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	74.298us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.076h	552.144ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.071m	429.299ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.470m	62.041ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.876m	150.124ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.685m	61.380ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.935m	83.650ms	5	5	100.00
		kmac_test_vectors_shake_128	45.105m	215.329ms	5	5	100.00
		kmac_test_vectors_shake_256	33.316m	259.917ms	5	5	100.00
		kmac_test_vectors_kmac	3.540s	90.891us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.390s	83.494us	5	5	100.00
V2	sideload	kmac_sideload	8.723m	21.103ms	50	50	100.00
V2	app	kmac_app	6.340m	27.490ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.576m	21.376ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.451m	43.281ms	50	50	100.00
V2	error	kmac_error	7.570m	99.069ms	50	50	100.00
V2	key_error	kmac_key_error	21.000s	20.130ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.310s	135.145us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.230s	1.470ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.260s	5.532ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.237m	6.083ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.110s	3.202ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.040m	75.756ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.180s	89.606us	50	50	100.00
V2	alert_test	kmac_alert_test	1.240s	21.149us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.890s	550.288us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.890s	550.288us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.320s	74.911us	5	5	100.00
		kmac_csr_rw	1.440s	33.560us	20	20	100.00
		kmac_csr_aliasing	7.790s	493.351us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	125.304us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.320s	74.911us	5	5	100.00
		kmac_csr_rw	1.440s	33.560us	20	20	100.00
		kmac_csr_aliasing	7.790s	493.351us	5	5	100.00
		kmac_same_csr_outstanding	2.630s	125.304us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.220s	224.686us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.220s	224.686us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.220s	224.686us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.220s	224.686us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.360s	256.997us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.636m	34.565ms	5	5	100.00
		kmac_tl_intg_err	4.260s	459.551us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.260s	459.551us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.110s	3.202ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.230m	3.042ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.723m	21.103ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.220s	224.686us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.636m	34.565ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.636m	34.565ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.636m	34.565ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.230m	3.042ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.110s	3.202ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.636m	34.565ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.864m	11.217ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.230m	3.042ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.219m	17.602ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			938	940	99.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.35	99.27	94.45	99.89	80.99	97.15	97.83	97.86

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_burst_write has 1 failures.

    • 7.kmac_burst_write.86158902776730626445645083110273591116863411646173141724066076012360984051948
      Line 248, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_burst_write/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_smoke has 1 failures.

    • 47.kmac_smoke.11342636777225281487804019051749466553403155281943481114090815928902061966934
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/47.kmac_smoke/latest/run.log

        UVM_ERROR @ 164442142 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 164442142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---