8c9ab41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.175m | 17.053ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.360s | 31.353us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.400s | 70.350us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 15.450s | 1.518ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.840s | 4.200ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.700s | 358.467us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.400s | 70.350us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.840s | 4.200ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.070s | 14.542us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.620s | 70.262us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 46.677m | 419.005ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 14.255m | 141.807ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 35.362m | 100.622ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 31.163m | 87.832ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 15.845m | 57.540ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 15.475m | 195.696ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 42.721m | 267.888ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 21.716m | 32.847ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 2.330s | 262.508us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.040s | 98.323us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 7.392m | 70.477ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.833m | 16.815ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.574m | 17.696ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 4.420m | 78.464ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 6.850m | 68.860ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 13.570s | 7.735ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.041m | 10.009ms | 32 | 50 | 64.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 34.190s | 1.319ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 40.260s | 2.033ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 52.110s | 40.490ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 44.650s | 943.697us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 33.395m | 88.474ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.120s | 15.671us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.310s | 281.903us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.600s | 558.412us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.600s | 558.412us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.360s | 31.353us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.400s | 70.350us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.840s | 4.200ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.960s | 191.198us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.360s | 31.353us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.400s | 70.350us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.840s | 4.200ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.960s | 191.198us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 722 | 740 | 97.57 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.720s | 122.592us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.720s | 122.592us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.720s | 122.592us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.720s | 122.592us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.410s | 256.130us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.194m | 12.550ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.520s | 441.599us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.520s | 441.599us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 44.650s | 943.697us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.175m | 17.053ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 7.392m | 70.477ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.720s | 122.592us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.194m | 12.550ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.194m | 12.550ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.194m | 12.550ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.175m | 17.053ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 44.650s | 943.697us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.194m | 12.550ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.932m | 68.029ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.175m | 17.053ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 2.503m | 11.771ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 917 | 940 | 97.55 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.89 | 97.69 | 94.44 | 100.00 | 75.21 | 96.04 | 97.74 | 96.12 |
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
9.kmac_sideload_invalid.25053780928818658194334905272869153328577162449270274872139986411208620165456
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10016416390 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x891a8000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10016416390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.kmac_sideload_invalid.42894744889360197486404258167835840926748090349988451795121473123040784909295
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10008976202 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1814a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008976202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
3.kmac_stress_all_with_rand_reset.103042410886529855587644637475784681055432316951454742525751784216751291956266
Line 97, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5517313678 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5517313678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.19211578888848145114127671511369318727322604981027853479227408846270372168764
Line 207, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3849222576 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3849222576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 3 failures:
20.kmac_sideload_invalid.112900279815569424910364639108553888149123055456802002869808036415843241135619
Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10144669239 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9a6de000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10144669239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.kmac_sideload_invalid.78722308490553260073599076717910835243479866169427961185329466349340389034164
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10041531247 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xadd0a000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10041531247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
4.kmac_stress_all_with_rand_reset.59827120502842596271556135409637685115504619569592681562809470163854192885245
Line 343, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3065995826 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3065995826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_stress_all_with_rand_reset.20415434683397107442422321125660347570070049448310421814380405548965738639097
Line 371, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4459697676 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4459697676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 2 failures:
26.kmac_sideload_invalid.47584392347097840207244462196920080627425265719743579760594329204668569109843
Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10259600355 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1c65b000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10259600355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.kmac_sideload_invalid.18381515607989420744094743521398724746041060152342186734723899699743451289998
Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10166779518 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x33950000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10166779518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
29.kmac_sideload_invalid.82852828077989099308760156332800722892567006080823991471226850197864743883092
Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10084612424 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd05f6000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10084612424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.kmac_sideload_invalid.33752011806606116200005140914069544431737901064910512404969049487660618191741
Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10200172636 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x78c50000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10200172636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
3.kmac_sideload_invalid.6527637122771792200991959089115809712028963233214980173995959555016160961562
Line 95, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 12466078960 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x299a9000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 12466078960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
7.kmac_sideload_invalid.33684978805337205945238751081265230764176404899737293009298545581810323664723
Line 98, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10362444186 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1ee8f000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10362444186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
12.kmac_sideload_invalid.62080836573918810684454396687379664625923631747794636417857582448174056498715
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10022172544 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdbda2000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10022172544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
36.kmac_sideload_invalid.42282595950870307007210326926959157606217332837312478464898341683310745409647
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10112272269 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x90e45000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10112272269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
38.kmac_sideload_invalid.59985834198270597145814192656411987225271435931075974783459775135378540236928
Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10583931774 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b509000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10583931774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
39.kmac_sideload_invalid.19984406408191736687112789506005755857994915173636262818363962671304860039845
Line 85, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10218606075 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x29ad3000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10218606075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---