OTBN Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 138.192us 0 1 0.00
V1 single_binary otbn_single 36.000s 121.810us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 9.000s 84.401us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 12.578us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 15.000s 121.941us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 9.000s 66.979us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 11.000s 45.355us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 12.578us 20 20 100.00
otbn_csr_aliasing 9.000s 66.979us 5 5 100.00
V1 mem_walk otbn_mem_walk 52.000s 6.667ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 26.000s 459.765us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 46.000s 158.026us 0 10 0.00
V2 multi_error otbn_multi_err 52.000s 573.979us 0 1 0.00
V2 back_to_back otbn_multi 7.250m 6.326ms 0 10 0.00
V2 stress_all otbn_stress_all 1.633m 306.089us 0 10 0.00
V2 lc_escalation otbn_escalate 35.000s 122.981us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 64.753us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 1.767m 475.353us 0 10 0.00
V2 alert_test otbn_alert_test 11.000s 26.527us 50 50 100.00
V2 intr_test otbn_intr_test 10.000s 16.784us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 80.844us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 80.844us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 9.000s 84.401us 5 5 100.00
otbn_csr_rw 8.000s 12.578us 20 20 100.00
otbn_csr_aliasing 9.000s 66.979us 5 5 100.00
otbn_same_csr_outstanding 8.000s 17.123us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 9.000s 84.401us 5 5 100.00
otbn_csr_rw 8.000s 12.578us 20 20 100.00
otbn_csr_aliasing 9.000s 66.979us 5 5 100.00
otbn_same_csr_outstanding 8.000s 17.123us 20 20 100.00
V2 TOTAL 162 246 65.85
V2S mem_integrity otbn_imem_err 12.000s 30.374us 2 10 20.00
otbn_dmem_err 17.000s 43.893us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 13.000s 66.791us 0 5 0.00
otbn_controller_ispr_rdata_err 10.000s 137.420us 0 5 0.00
otbn_mac_bignum_acc_err 17.000s 36.172us 0 5 0.00
otbn_urnd_err 5.000s 29.081us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 19.961us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 32.702us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 67.767us 10 10 100.00
V2S tl_intg_err otbn_sec_cm 4.150m 1.112ms 4 5 80.00
otbn_tl_intg_err 45.000s 215.476us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 31.000s 197.001us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S prim_count_check otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 138.192us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 17.000s 43.893us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 30.374us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 45.000s 215.476us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 35.000s 122.981us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 30.374us 2 10 20.00
otbn_dmem_err 17.000s 43.893us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 64.753us 4 5 80.00
otbn_illegal_mem_acc 6.000s 19.961us 4 5 80.00
otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_scramble_key_sideload otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 30.374us 2 10 20.00
otbn_dmem_err 17.000s 43.893us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 64.753us 4 5 80.00
otbn_illegal_mem_acc 6.000s 19.961us 4 5 80.00
otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 35.000s 122.981us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 30.374us 2 10 20.00
otbn_dmem_err 17.000s 43.893us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 64.753us 4 5 80.00
otbn_illegal_mem_acc 6.000s 19.961us 4 5 80.00
otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_data_reg_sw_sca otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 8.000s 22.299us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 29.948us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 55.000s 788.267us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 55.000s 788.267us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 12.000s 80.384us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 13.000s 68.981us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 25.370us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 25.370us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 8.000s 10.594us 4 7 57.14
V2S sec_cm_data_mem_sec_wipe otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 7.250m 6.326ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 18.000s 135.575us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 36.000s 121.810us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.150m 1.112ms 4 5 80.00
V2S TOTAL 72 163 44.17
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 8.717m 1.908ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 299 585 51.11

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.53 98.06 75.01 97.26 79.09 64.90 87.18 80.79 98.72

Failure Buckets