ROM_CTRL/32KB Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.900s	320.782us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.020s	440.822us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.150s	556.317us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.190s	553.355us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.170s	557.579us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.380s	188.204us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.150s	556.317us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	557.579us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.340s	172.009us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.950s	283.420us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.990s	486.792us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	26.650s	1.600ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.750s	568.376us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.380s	554.207us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.110s	176.084us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.110s	176.084us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.020s	440.822us	5	5	100.00
		rom_ctrl_csr_rw	9.150s	556.317us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	557.579us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.230s	186.063us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.020s	440.822us	5	5	100.00
		rom_ctrl_csr_rw	9.150s	556.317us	20	20	100.00
		rom_ctrl_csr_aliasing	5.170s	557.579us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.230s	186.063us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	34.640s	3.130ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
		rom_ctrl_tl_intg_err	1.091m	534.205us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.900s	320.782us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.900s	320.782us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.900s	320.782us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.091m	534.205us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
		rom_ctrl_kmac_err_chk	12.750s	568.376us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.447m	2.752ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	34.640s	3.130ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.037m	628.911us	2	5	40.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.391m	8.522ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

1.rom_ctrl_sec_cm.105646953479563237072662718611909079473650427688816247485014997945750418072119
Line 171, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18469038ps failed at 18469038ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18489038ps failed at 18489038ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

2.rom_ctrl_sec_cm.16953648756380439076531544359069044304965776424186252173513837996412675941938
Line 482, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 121900385ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 121900385ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 121900385ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.70947089384890465605608563170672745533844571130376975184297427241026705792916
    Line 99, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 3732607509 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 3732607509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.rom_ctrl_corrupt_sig_fatal_chk.11505305351236823841814053076293708948715280641625621802992881403092716023167
    Line 98, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 660864034 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 660864034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

0.rom_ctrl_sec_cm.80323479258630498790686114253176213003510953154276024466233861704637712248552
Line 177, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 24610308ps failed at 24610308ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 24610308ps failed at 24610308ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'