ROM_CTRL/64KB Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.640s	298.297us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	20.330s	307.194us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.220s	300.505us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.610s	3.988ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.690s	534.260us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.120s	1.044ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.220s	300.505us	20	20	100.00
		rom_ctrl_csr_aliasing	11.690s	534.260us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.130s	302.105us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.470s	727.433us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.360s	309.094us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	54.840s	1.086ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	24.470s	2.783ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	15.930s	1.061ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.760s	1.586ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.760s	1.586ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	20.330s	307.194us	5	5	100.00
		rom_ctrl_csr_rw	12.220s	300.505us	20	20	100.00
		rom_ctrl_csr_aliasing	11.690s	534.260us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.610s	397.507us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	20.330s	307.194us	5	5	100.00
		rom_ctrl_csr_rw	12.220s	300.505us	20	20	100.00
		rom_ctrl_csr_aliasing	11.690s	534.260us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.610s	397.507us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.348m	6.411ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
		rom_ctrl_tl_intg_err	2.331m	1.417ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.640s	298.297us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.640s	298.297us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.640s	298.297us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.331m	1.417ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
		rom_ctrl_kmac_err_chk	24.470s	2.783ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.226m	17.427ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.348m	6.411ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.922m	1.066ms	1	5	20.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.837m	4.193ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.59990481739098656522935070098403784543745916209902170738587865035973896259772
      Line 182, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 31611352ps failed at 31611352ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 31611352ps failed at 31611352ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 4.rom_ctrl_sec_cm.20711158343572283719194524185680142665484281187232057102273072332305560027940
      Line 166, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26656995ps failed at 26656995ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26656995ps failed at 26656995ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 1.rom_ctrl_sec_cm.65900139703324902864745166560850894676932238929103925071861487302807516605710
      Line 166, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 34143614ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 34143614ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 34143614ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.112559460370440796334713234239851527367560813645963989009425777187747165854676
      Line 300, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26153850ps failed at 26153850ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26169979ps failed at 26169979ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'