RV_TIMER Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.260s	1.044ms	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.750s	187.974us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.770s	56.540us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.040s	416.731us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.810s	103.630us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.510s	39.296us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.770s	56.540us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	103.630us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	13.070s	1.570ms	3	20	15.00
V2	disabled	rv_timer_disabled	3.600s	2.568ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.863m	3.017s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.863m	3.017s	10	10	100.00
V2	stress	rv_timer_stress_all	6.170s	4.989ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.860s	18.998us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.770s	13.796us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.290s	420.903us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.290s	420.903us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.750s	187.974us	5	5	100.00
		rv_timer_csr_rw	0.770s	56.540us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	103.630us	5	5	100.00
		rv_timer_same_csr_outstanding	1.080s	64.817us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.750s	187.974us	5	5	100.00
		rv_timer_csr_rw	0.770s	56.540us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	103.630us	5	5	100.00
		rv_timer_same_csr_outstanding	1.080s	64.817us	20	20	100.00
V2		TOTAL			193	210	91.90
V2S	tl_intg_err	rv_timer_sec_cm	1.460s	355.469us	5	5	100.00
		rv_timer_tl_intg_err	1.380s	82.427us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.380s	82.427us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.130s	282.267us	4	10	40.00
V3	max_value	rv_timer_max	1.660s	163.076us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	53.510s	6.209ms	16	20	80.00
V3		TOTAL			20	40	50.00
		TOTAL			313	350	89.43

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 23 failures:
- Test rv_timer_min has 6 failures.
  - 0.rv_timer_min.41952537354152752048894223091266344626489003288663293891646869823607830780270
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 282267072 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcb47c904) == 0x1
  UVM_INFO @ 282267072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_min.3787467927559436585855482619809614607815758127056196022932730374862840901882
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 326985951 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf72d3f04) == 0x1
  UVM_INFO @ 326985951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
- Test rv_timer_random_reset has 17 failures.
  - 0.rv_timer_random_reset.6882392658641019580975645740268231320865814490954938995896239251877932193146
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1569660418 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd9759504) == 0x1
  UVM_INFO @ 1569660418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.69217470474336435737087489382993654856480798635136532011756484553135009362794
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 989504064 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6fd52504) == 0x1
  UVM_INFO @ 989504064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.2529055221958641255894134843521889934460396880963893612146524388044084584251
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  47135913 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  47135913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.65724177458660503274170155713323530689340619914781895828652544295780628977826
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  90121202 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  90121202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test rv_timer_stress_all_with_rand_reset has 3 failures.

0.rv_timer_stress_all_with_rand_reset.78001088521229388101288466051298090408801219617682848586800291591726440317664
Line 241, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1591948870 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1591948870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rv_timer_stress_all_with_rand_reset.83908379154618279606218398176593104359676046627416617341394203319005724964843
Line 238, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6377634643 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6377634643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 6.rv_timer_stress_all_with_rand_reset.25758572278298700642629200171204517023941431862892613473481752741130582023264
    Line 288, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5475027875 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 5475027875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 7.rv_timer_max.106553611259184215894713614786422961351320098180609733765676277303903704795746
    Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/7.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 163075769 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @ 163075769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```