SPI_DEVICE/1R1W Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.160m	64.709ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.770s	154.043us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.900s	110.928us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.960s	3.485ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.310s	1.241ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.100s	1.026ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.900s	110.928us	20	20	100.00
		spi_device_csr_aliasing	19.310s	1.241ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	10.392us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.580s	26.616us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.190s	19.029us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	2.442us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.060s	3.286us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	11.400s	521.676us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.400s	521.676us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.340s	8.058ms	50	50	100.00
		spi_device_tpm_sts_read	1.670s	143.923us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.400s	27.072ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.470s	27.328ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.650s	20.921ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.650s	20.921ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.780s	10.818ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.780s	10.818ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.780s	10.818ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.780s	10.818ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.780s	10.818ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	32.440s	29.181ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.697m	12.087ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.697m	12.087ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.697m	12.087ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.600s	18.597ms	50	50	100.00
		spi_device_read_buffer_direct	17.460s	1.572ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.697m	12.087ms	50	50	100.00
		spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.744m	67.101ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.260s	4.438ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.260s	4.438ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.160m	64.709ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.070m	129.080ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.110m	163.830ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	54.953us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	17.516us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.400s	729.031us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.400s	729.031us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.770s	154.043us	5	5	100.00
		spi_device_csr_rw	2.900s	110.928us	20	20	100.00
		spi_device_csr_aliasing	19.310s	1.241ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	1.171ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.770s	154.043us	5	5	100.00
		spi_device_csr_rw	2.900s	110.928us	20	20	100.00
		spi_device_csr_aliasing	19.310s	1.241ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	1.171ms	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.580s	252.807us	5	5	100.00
		spi_device_tl_intg_err	22.770s	1.032ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.770s	1.032ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.713m	73.459ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	99.11	96.57	71.19	89.36	98.40	94.43	99.21

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.17735251186644761462446145385709140527919135651727285367075395134868538178036
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2184841 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[91])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2184841 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2184841 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.113370770129216495424737899988078977215323635469362026078885509520007351962060
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    932901 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[69])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    932901 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    932901 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[965])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.38220173764432914654697911136471305889473184587709729623210115060146699447825
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    847454 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd0ddfc [110100001101110111111100] vs 0x0 [0])
        UVM_ERROR @    869454 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd6b8a8 [110101101011100010101000] vs 0x0 [0])
        UVM_ERROR @    912454 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x476351 [10001110110001101010001] vs 0x0 [0])
        UVM_ERROR @    925454 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ec6e1 [111101100011011100001] vs 0x0 [0])
        UVM_ERROR @    997454 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x528a10 [10100101000101000010000] vs 0x0 [0])