SPI_HOST Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.500m	15.440ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	68.805us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	54.585us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	324.972us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	34.292us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	24.286us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	54.585us	20	20	100.00
		spi_host_csr_aliasing	2.000s	34.292us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.595us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	17.599us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	47.230us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	21.000s	4.120ms	50	50	100.00
		spi_host_error_cmd	2.000s	23.168us	50	50	100.00
		spi_host_event	6.733m	26.653ms	50	50	100.00
V2	clock_rate	spi_host_speed	8.000s	561.178us	50	50	100.00
V2	speed	spi_host_speed	8.000s	561.178us	50	50	100.00
V2	chip_select_timing	spi_host_speed	8.000s	561.178us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.517m	53.445ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	76.119us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.000s	561.178us	50	50	100.00
V2	full_cycle	spi_host_speed	8.000s	561.178us	50	50	100.00
V2	duplex	spi_host_smoke	1.500m	15.440ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.500m	15.440ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.683m	5.237ms	50	50	100.00
V2	spien	spi_host_spien	3.033m	21.901ms	50	50	100.00
V2	stall	spi_host_status_stall	27.783m	213.281ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	53.000s	10.756ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	21.000s	4.120ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	17.455us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	70.174us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	80.049us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	80.049us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	68.805us	5	5	100.00
		spi_host_csr_rw	2.000s	54.585us	20	20	100.00
		spi_host_csr_aliasing	2.000s	34.292us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	46.417us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	68.805us	5	5	100.00
		spi_host_csr_rw	2.000s	54.585us	20	20	100.00
		spi_host_csr_aliasing	2.000s	34.292us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	46.417us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	92.357us	20	20	100.00
		spi_host_sec_cm	2.000s	140.087us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	92.357us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.683m	48.705ms	10	10	100.00
		TOTAL			839	840	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.10	96.82	93.35	98.69	94.35	73.07	100.00	95.21	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_status_stall has 1 failures.

    • 24.spi_host_status_stall.33353028932704717637933158995598012989637443576778355762760279517184018648622
      Line 817, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---