SRAM_CTRL/MAIN Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.579m	896.299us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	17.490us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	46.762us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.680s	580.145us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.130s	19.184us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.300s	2.656ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	46.762us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	19.184us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.362m	13.833ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.978m	11.134ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.701m	42.588ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.378m	5.541ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	40.800m	1.569s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.632m	20.511ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.497m	153.775ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.617m	27.119ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.860m	3.538ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.328m	133.899ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.634m	1.567ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.556m	825.374us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.781m	3.674ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.421m	202.679ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.830s	6.687ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.819h	326.938ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	14.167us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.910s	750.161us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.910s	750.161us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	17.490us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	46.762us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	19.184us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.190s	82.106us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	17.490us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	46.762us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	19.184us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.190s	82.106us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	58.350s	28.399ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
		sram_ctrl_tl_intg_err	3.650s	853.581us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.650s	853.581us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.421m	202.679ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	25.421m	202.679ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	46.762us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.617m	27.119ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.617m	27.119ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.617m	27.119ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.497m	153.775ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.140s	13.396ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	58.350s	28.399ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.190s	7.296ms	28	50	56.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.579m	896.299us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.579m	896.299us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.617m	27.119ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.497m	153.775ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.579m	896.299us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.200s	20.843us	0	5	0.00
V2S		TOTAL			112	145	77.24
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.965m	8.016ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1157	1190	97.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 21 failures:
- Test sram_ctrl_readback_err has 21 failures.
  - 9.sram_ctrl_readback_err.44539786842309621938925487865973955940919933420531424659439960694437327298777
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2794698938 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x3d)
  UVM_INFO @ 2794698938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.sram_ctrl_readback_err.95813270461803470037492261493166771433667695776970195222167024289193706289312
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 1342855869 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x37)
  UVM_INFO @ 1342855869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
Offending 'reqfifo_rvalid' has 6 failures:
- Test sram_ctrl_mubi_enc_err has 6 failures.
  - 14.sram_ctrl_mubi_enc_err.2624648601375977147111390191914937467143520331863117289362826215634533800518
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2631646716 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2631646716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.sram_ctrl_mubi_enc_err.65257668099472114899091520599722285329658994190574414986146234741899699186119
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/17.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 669635536 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 669635536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
- Test sram_ctrl_sec_cm has 4 failures.
  - 0.sram_ctrl_sec_cm.65422113493120173588001990581619197426122817646707225100865606147214488584384
    Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  20843061 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  20843061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.sram_ctrl_sec_cm.106534045119531511013537886951374940505146492082975001611712731892989707423122
    Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   6693800 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   6693800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 1.sram_ctrl_sec_cm.7302532974421785852922029872761107106990908173505766632133842715545925791606
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   3534310 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3534310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3818) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

39.sram_ctrl_readback_err.67139890634984981438048595230714267055411420325851556939398438418920360902297
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/39.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @ 677394173 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3818) { a_addr: 'h9635e78  a_data: 'h15  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb1  a_opcode: 'h0  a_user: 'h25248  d_param: 'h0  d_source: 'hb1  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 677394173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---