SRAM_CTRL/RET Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.703m	3.644ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.070s	14.819us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.090s	96.096us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.760s	430.533us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	17.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.360s	89.308us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.090s	96.096us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	17.939us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.850s	7.373ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.870s	338.945us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	18.567m	27.850ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.311m	16.214ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.686m	29.276ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.377m	40.933ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.500s	2.478ms	50	50	100.00
V2	executable	sram_ctrl_executable	22.866m	87.993ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.303m	796.541us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.735m	205.779ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.459m	519.256us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.566m	305.852us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.784m	1.107ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.595m	53.059ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.250s	42.832us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.042h	17.830ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	14.848us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.440s	171.732us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.440s	171.732us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.070s	14.819us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	96.096us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	17.939us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	191.340us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.070s	14.819us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	96.096us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	17.939us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	191.340us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.970s	1.163ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
		sram_ctrl_tl_intg_err	3.320s	683.042us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.320s	683.042us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.595m	53.059ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.595m	53.059ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.090s	96.096us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	22.866m	87.993ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	22.866m	87.993ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	22.866m	87.993ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.500s	2.478ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.680s	171.250us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.970s	1.163ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.640s	119.713us	33	50	66.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.703m	3.644ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.703m	3.644ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	22.866m	87.993ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.500s	2.478ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.703m	3.644ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.990s	7.300us	0	5	0.00
V2S		TOTAL			118	145	81.38
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.325m	15.311ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1162	1190	97.65

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 17 failures:

  • Test sram_ctrl_readback_err has 17 failures.

    • 0.sram_ctrl_readback_err.102911023352761449302782075743878601958256033877919251078031370811532794143069
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  27745484 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x39) != exp (0x2f)
        UVM_INFO @  27745484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_readback_err.93902734025997232392842669574368516564552760291629929723260740857024135231925
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  44015624 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7e) != exp (0x6f)
        UVM_INFO @  44015624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 15 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 16.sram_ctrl_mubi_enc_err.42474039565309318488161826786368351116710573602925692388842468796031754657211
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  28222170 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  28222170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 19.sram_ctrl_mubi_enc_err.54842899981998785799086155046901211419292839402631203582525308531570951610211
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  98887523 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  98887523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.78911425269756438483069416412149371183206686711880807079580952205798750678212
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3941091 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3941091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.99811973992624440806376642882936988516645762782053455587189018198517009391015
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1703258 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1703258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.9602354561599444205877940364096700317386998000810795769300666426049004310013
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4700563 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4700563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.100687851998538180552075517492899444875946842336979746464581124853786822845234
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   7299743 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7299743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 11.sram_ctrl_csr_mem_rw_with_rand_reset.111983683005988203416010023917907792601162492436430759828132966176460502985164
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  89308191 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  89308191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---