CHIP Simulation Results

Friday October 17 2025 17:10:00 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.908m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.908m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.311m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.624m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.039m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.961m	5.978ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.961m	5.978ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.961m	5.978ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.520s	10.300us	0	3	0.00
		chip_sw_example_manufacturer	2.799m		0	3	0.00
		chip_sw_example_concurrency	7.010m	4.891ms	3	3	100.00
		chip_sw_uart_smoketest_signed	17.350s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	16.120s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	14.170s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.170s		0	3	0.00
V1	xbar_smoke	xbar_smoke	37.320s	64.352us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.678m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.599m	8.469ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.276m	4.220ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.691m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	42.440s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	50.016s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	50.557s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.610s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.610s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.080m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.964m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.339m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.339m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.399m	3.804ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.397m	3.503ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	10.077m	14.932ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	17.410s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	18.241s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	19.177m	26.098ms	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	9.763m	6.376ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.532m	18.027ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.532m	18.027ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	24.378s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.816m	5.340ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.816m	5.340ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.100m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.330m	5.461ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.610m	6.297ms	3	3	100.00
		chip_sw_aes_idle	7.123m	5.252ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.635m	4.760ms	3	3	100.00
		chip_sw_kmac_idle	5.845m	3.811ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	23.627m	12.019ms	1	3	33.33
		chip_sw_clkmgr_off_hmac_trans	25.404m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	25.221m	11.954ms	1	3	33.33
		chip_sw_clkmgr_off_otbn_trans	22.795m	12.019ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	19.181s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.569s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.697s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.674s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.056s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.105s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.555s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	19.181s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.569s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.697s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.674s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.056s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.105s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.555s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	23.744s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.056m	10.160us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.030m	10.180us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.009m	10.340us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	54.050s	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.589s		0	3	0.00
		chip_sw_clkmgr_jitter	5.186m	5.421ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	6.067m	5.419ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	30.070s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	53.200s	10.340us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.096m	10.140us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	54.950s	10.260us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	59.480s	10.140us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.020m	10.280us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.150s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	20.796s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.693s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	20.761s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	17.209m	16.587ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.816m	5.340ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	1.193m		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	17.209m	16.587ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	29.925s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.025m		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	26.814s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	31.303s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.203m		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	10.077m	14.932ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	45.374m	20.019ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.616m	8.170ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.302m	10.612ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.820m	4.870ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	17.999s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	51.664s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.320s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.302m	10.612ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	18.521s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	22.361s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	29.378s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	25.188s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	25.830s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	19.084s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	51.664s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	25.220s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	10.006m	10.557ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.862s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.106s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.211s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	43.090s		0	3	0.00
		chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	11.713m	9.029ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	17.078m	15.142ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	19.063s		0	3	0.00
		chip_prim_tl_access	17.228m	25.768ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	19.181s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.569s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.697s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.674s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.056s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.105s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.555s		0	3	0.00
		chip_rv_dm_lc_disabled	19.177m	26.098ms	1	3	33.33
V2	chip_sw_aes_enc	chip_sw_aes_enc	7.315m	6.029ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.056m	10.160us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.790m	3.805ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	7.123m	5.252ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.927m	4.796ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.030m	10.180us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.635m	4.760ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.541m	5.388ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.400m	5.422ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	54.050s	10.280us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	11.713m	9.029ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	44.040s	10.380us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.056m	5.730ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.845m	3.811ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	22.718s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	22.718s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.129s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.608m	5.209ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.772s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	11.713m	9.029ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.009m	10.340us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	34.199s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	23.744s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.610m	6.297ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.610m	6.297ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.610m	6.297ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.875m	5.619ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	17.078m	15.142ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	17.078m	15.142ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.525m	10.342ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.589s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	19.063s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
		chip_sw_data_integrity_escalation	2.339m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.875m	5.619ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.713m	9.029ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.525m	10.342ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.876m	5.075ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.875m	5.619ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.713m	9.029ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.525m	10.342ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.876m	5.075ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.370s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	25.220s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.862s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.106s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.211s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	43.090s		0	3	0.00
		chip_sw_lc_ctrl_transition	23.357s		0	15	0.00
		chip_prim_tl_access	17.228m	25.768ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	17.228m	25.768ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	16.495s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	20.715s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	20.796s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	23.744s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.056m	10.160us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.030m	10.180us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.009m	10.340us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	54.050s	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.589s		0	3	0.00
		chip_sw_clkmgr_jitter	5.186m	5.421ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	12.239m	10.153ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	12.239m	10.153ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	8.059m	6.185ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.741m	5.131ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	6.857m	5.559ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	11.476m	5.918ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.176m	5.442ms	2	3	66.67
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	7.484m	4.552ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.876m	5.075ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	45.374m	20.019ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	45.374m	20.019ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.808m	5.216ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.142m	6.095ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.500m	3.853ms	3	3	100.00
		chip_sw_csrng_smoketest	6.412m	4.387ms	3	3	100.00
		chip_sw_gpio_smoketest	6.256m	4.123ms	3	3	100.00
		chip_sw_hmac_smoketest	7.876m	5.363ms	3	3	100.00
		chip_sw_kmac_smoketest	7.695m	5.221ms	3	3	100.00
		chip_sw_otbn_smoketest	8.335m	5.876ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.482m	4.368ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.824m	5.198ms	3	3	100.00
		chip_sw_rv_timer_smoketest	9.393m	6.057ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.238m	4.912ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.415m	5.194ms	3	3	100.00
		chip_sw_uart_smoketest	7.138m	4.588ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	17.806s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	17.350s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.678m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	18.894s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.182m	4.384ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.357m	4.209ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.436m	4.342ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	6.359m	5.644ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.617s		0	3	0.00
		chip_rv_dm_lc_disabled	19.177m	26.098ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	17.531s		0	3	0.00
		chip_sw_lc_walkthrough_prod	19.080s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	53.859s		0	3	0.00
		chip_sw_lc_walkthrough_rma	18.476s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	17.617s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	27.909s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.659m		0	3	0.00
		rom_volatile_raw_unlock	17.038s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	17.408s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.219m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.767m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.790m	4.712ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	7.790m	4.712ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.170s		0	3	0.00
		chip_same_csr_outstanding	15.480s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.170s		0	3	0.00
		chip_same_csr_outstanding	15.480s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.381m	528.377us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.490s	12.672us	100	100	100.00
		xbar_smoke_large_delays	8.997m	2.766ms	100	100	100.00
		xbar_smoke_slow_rsp	11.020m	2.303ms	100	100	100.00
		xbar_random_zero_delays	2.239m	83.832us	100	100	100.00
		xbar_random_large_delays	34.435m	12.969ms	100	100	100.00
		xbar_random_slow_rsp	54.090m	14.215ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	3.461m	263.343us	100	100	100.00
		xbar_error_and_unmapped_addr	2.470m	208.536us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	5.031m	538.095us	100	100	100.00
		xbar_error_and_unmapped_addr	2.470m	208.536us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.720m	826.584us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.049m	17.406ms	75	100	75.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.631m	401.719us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	38.737m	4.495ms	100	100	100.00
		xbar_stress_all_with_error	30.456m	3.685ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	53.725m	1.755ms	97	100	97.00
		xbar_stress_all_with_reset_error	58.297m	6.520ms	99	100	99.00
V2	rom_e2e_smoke	rom_e2e_smoke	19.130s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.997s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	19.601s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	17.115s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	18.746s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	19.429s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.817s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	17.274s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.191s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.991s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.990s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.624s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	15.953s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.596m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.632m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.170m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.615m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.285m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.452m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.517m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.354m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.164m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.215m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	1.300m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.510m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.098m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.359m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	46.043s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.077s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.827s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	20.871s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.657s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.331s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	20.782s		0	3	0.00
		rom_e2e_asm_init_dev	19.145s		0	3	0.00
		rom_e2e_asm_init_prod	19.833s		0	3	0.00
		rom_e2e_asm_init_prod_end	18.915s		0	3	0.00
		rom_e2e_asm_init_rma	18.611s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	19.267s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	19.781s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.416s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	18.858s		0	3	0.00
V2		TOTAL			1895	2429	78.02
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.727m	4.488ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	6.821m	5.375ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	14.257s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.262s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.628s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	18.788s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	38.827m	16.614ms	90	100	90.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.510s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	30.959m	16.141ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	18.102s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.751s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	14.257s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.262s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.628s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	16.060s		0	1	0.00
		rom_e2e_jtag_inject_dev	13.954s		0	1	0.00
		rom_e2e_jtag_inject_rma	15.780s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.616s		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	31.589m	15.632ms	3	3	100.00
		chip_sw_entropy_src_kat_test	7.083m	5.663ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.693m	4.258ms	3	3	100.00
		chip_plic_all_irqs_0	13.976m	6.670ms	3	3	100.00
		chip_plic_all_irqs_10	15.282m	6.138ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.093m	6.073ms	3	3	100.00
		chip_sw_dma_abort	6.489m	4.761ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	18.324s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	18.757s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.852s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	17.677s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.812s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	19.062s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	16.503s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	19.215s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	17.412s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	18.099s		0	3	0.00
		chip_sw_entropy_src_smoketest	6.970m	5.627ms	3	3	100.00
		chip_sw_mbx_smoketest	7.722m	5.014ms	3	3	100.00
		TOTAL			2032	2668	76.16

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
72.59	73.86	78.18	63.43	57.14	80.94	67.67	86.91

Failure Buckets

Job returned non-zero exit code has 455 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.37334653818392785288759609006439830491904360615411194479743488026059433873174
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 148.807s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.105319715682753334881302354323792337164087607688244485454979052638241305708674
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 32.731s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.37728052422920500434206882636690698191510084731572340820305939798871169728829
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 122.260s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.24347625997848230759385288810295925706459928893127677011340103103421738813180
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 19.714s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.4081242184601517038437373601278809088892191049114051111698617586463683830737
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.790s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.8631831379212120838192876248461005726098098673196558142691309406812196625078
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 29.589s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.111903210204073521908932547891310909806848257745236496743653462595787498817283
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 101.754s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.23422053842266268823528553778505757423898161117196108116361253131398551972536
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 22.659s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.108117548421504342017647429937581878264821059557906879078858788399798403200121
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 156.238s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.71646844583757503507349277959769755766382555702061613215152716140871860558928
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 8.732s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 131 more tests.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 29 failures:
- Test chip_tl_errors has 29 failures.
  - 0.chip_tl_errors.8249293741729007858313267021946442877387992004515278136530328488378970429301
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3512.490514 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3512.490514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_tl_errors.61555374244559152647318250632658238986565891123618255341759287741749535561344
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5306.618239 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5306.618239 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
Job timed out after * minutes has 29 failures:
- Test xbar_access_same_device_slow_rsp has 25 failures.
  - 0.xbar_access_same_device_slow_rsp.54636443191441045223880452888446462675889485747103484475358782157800215857565
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 12.xbar_access_same_device_slow_rsp.95455318156895297430684643082329377169192185691420738323828032139769171744223
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 23 more failures.
- Test xbar_stress_all_with_reset_error has 1 failures.
  - 10.xbar_stress_all_with_reset_error.82703331946052429618382166464010875746615176996540433976862661190618698122593
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
- Test xbar_stress_all_with_rand_reset has 3 failures.
  - 69.xbar_stress_all_with_rand_reset.14076118358084866768109763503320536055844592440313836213116882901946927119820
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 79.xbar_stress_all_with_rand_reset.92192689189212752853860951976892576620734202210600907130561704006560998172798
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.105392923527826483523008522195898902558703301228735027526819254160003868665465
    Line 466, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.61679803183080421191972015287211376327197100909266456902888801102202235953000
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.48910167091391582723876645359723529970486892992747517757571939322656046005807
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.35973940929413518422689659567872400498277310754420816703198921209279941578437
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.55943348923631523305899999535552017317625177619398179042195639912633121315772
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.43882105676991570378315357895721554195621865069718452837936775560625464225396
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.63220385884832366504916734705331148515942169784961199094220222816243256032693
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.68774754727838474907725585782755525259943205752217704915567719676836599230806
    Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.52280787227102092655905788365707299890099768854316935223640154278441337687133
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.39181900128233025826790074862721147235043519778491358613078018042663014054789
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 13 failures:

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.23808084479646433795600340199512278590884228438100108464718136615717712806782
Line 488, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.601253 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.601253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.47064371390656631879738869189463949998916961583982888072097171401781538459680
Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.930490 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.930490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.25992368231546332885573032684171966543760995828935879158012580447817049226222
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.839847 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.839847 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.105329456949985627725809746058306103656566141163801714201144767106494310620574
Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.928002 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.928002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.43521249985968909543942802687674070626984882750619641649664913976690736904047
Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.815121 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.815121 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.46706194155481269855827606407732257887089050726077677575624739328125631033688
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.558598 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.558598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test chip_sw_clkmgr_off_aes_trans has 2 failures.

1.chip_sw_clkmgr_off_aes_trans.54103164250463701386719665063661833395452882895707846995551547625033130135902
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.692649 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.692649 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_aes_trans.51980735880923290541898964313614980782300234658409066539255615495698319818222
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.426339 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.426339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.93610370735659907218532881880662258138909235428736355807835167231933420651295
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.30782510560545621427802568897704827549877896317825138322535564596560729685849
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.73860057486909440073826360198403918986622419673099721565171557825811376592355
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.1258629956166695556519800785218482774799597956025437939314285581665143622050
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.16646416304736392115601075835211207914095518505591266727200775119240870847463
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.107079104849097422966563316979752658002374605006629573353312998734263221220979
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.110371577321277808909478995262537448675765250247284523634690488885530991483938
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.81330776465934772014122947949820418006719821076992671785204205618122421779341
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.81396211995273051592621271345152731963888481181995214054711932167272116906214
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6163.809382 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11598207829155512138937432558817592386588712483549732500100859088985654424780276116417032722345812919793785842237006511550375282135323330504674929002503260 [0xdd72dbe4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35b246b157f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6163.809382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.7691319754687023394262079110160040058015490299115314950701584564106905392711
Line 439, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9029.284609 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (353780916175092094207781644202182994697053249160647844887011469980443097062907948068357140325967711430115156418194948443815960911033704234951881219464284 [0x6c13ebeaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd380978e4f7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9029.284609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.74236020036020346394077856817824061722223711737143495537738650781336995198094
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6001.702052 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10283175716435327363336825601451259684519932736447457413710184948337918844084024992002731154719761193973130803340351179417189960535856201880146713837395036 [0xc4571daaaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd34201ad5b7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6001.702052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.28104524169021956373436888207716022335264422631183795979366756146262126465500
Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7090.139421 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3737541293703493504952597625828009278488063226380624667885697228609711389335219214549833556066420622760023099584336020276798590648972185264357962112392284 [0x475cb8a6aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3c10a08577f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7090.139421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 6 failures:

Test chip_sw_clkmgr_off_hmac_trans has 2 failures.

0.chip_sw_clkmgr_off_hmac_trans.23913377220182347096328237529720755024339127617505631238454898060422236746999
Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.669839 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.669839 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_hmac_trans.14361584572271114679574422428000561026858928321381978938922197353613945581497
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.573909 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.573909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 2 failures.

0.chip_sw_clkmgr_off_kmac_trans.48763455080136798589609805178175191331379238039860612676428023221408169318362
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12027.017636 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12027.017636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_kmac_trans.106079571083950425891757247516129149628884737428036364778058482461616824197353
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.683716 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.683716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 2 failures.

0.chip_sw_clkmgr_off_otbn_trans.47957099078489953931381364291508462529506291630966740962077611597611010669911
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.532190 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.532190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_otbn_trans.105905049087468884691871490278593755463379227869871652123077371449281039819303
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.566442 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.566442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.87688127580034559316842712829436331416709504057869866785964656536411545837635
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4634.104959 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h4e30288a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h26936  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4634.104959 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.110634545968833208321228084112654682062103576000823091660804462184030734487269
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3062.356920 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h858d4a2a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h1  a_user: 'h248f2  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3062.356920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.104860113213998293222305175623362957164638534795441818381414440635909390700815
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4186.308228 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'hc21181c9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h2692e  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4186.308228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.31910748152677940989821044679857566078471257454427332566819577153951626706191
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3911.408208 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'heb305635  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h1  a_user: 'h248ed  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3911.408208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 2.chip_sw_all_escalation_resets.67968070152167077706853176162582860066210449877563556417943648839677865405680
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3749.063852 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
  UVM_INFO @ 3749.063852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.chip_sw_all_escalation_resets.39041420015674955236003572717227849647555304889437887412465925327439674274251
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3638.805448 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
  UVM_INFO @ 3638.805448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.110180763528059572607069326660279444302222354101129489300400235227760870602885
    Line 1371, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.103542755968983258938185281195473178490039468791647236791810224199892892470892
    Line 369, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.47785790261664237923376555675721763850174575113924194960504317424443074800520
    Line 474, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4220.273176 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4220.273176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.19526935074577186670040647453632899206373650451605084923422174410375629601463
    Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4618.010968 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4618.010968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.36966059100477325751258686075030979665935363911293274863956854117527028351603
    Line 687, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8330.534082 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8330.534082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.77748464489006534872830775118353441074875650885933038797966508353188111823995
    Line 631, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 5884.767050 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 5884.767050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.18015335470775312594714946605124865124580207601599442716191452235617319118922
Line 500, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4420.060473 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4420.060473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.67164018197407200616333267683891753519325133311702396649976183269660752962168
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 6184.505748 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 6184.505748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.59776877248150341832590122956125801063203123206356572112407501875290299188715
    Line 512, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4491.083780 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4491.083780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.71877880994365670077498644694130803906479185950554346552348104466628853932019
    Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5130.884060 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5130.884060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.8870491456768005483348069846923504781946300816863739993284026582493992203720
    Line 486, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3292.561946 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3292.561946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.101564542613080995326651377128739331566935445506447802653576073940925729277908
    Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5824.004065 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5824.004065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.95884914989586839348611330373136393095231264622127696750057937255776316662427
    Line 472, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6031.734110 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6031.734110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.45351098901556214373642379801271599357023996286719964388470621667755436892797
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5918.209115 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5918.209115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.18100053659933183841142810503594974236304615552237629073314002171507284483143
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.48021962788653940574225563902693534471975219158359230551663595154543537397276
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.14364740421617337015861117085579564148463882832575143287038003125998962144437
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13000.228336 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13000.228336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.92528786900899288124693904336289372665404740345884391601150627562131126039961
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13914.478192 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13914.478192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.65417614775596684396451609639598768036157925878027197566896433033856963137701
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4516.758474 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4516.758474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.29566778723201419552057366583539932864805168566174001873523532186323118845725
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 3731.099910 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3731.099910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 1.chip_sw_clkmgr_off_hmac_trans.42970057957599732066901640095433076533268115440202969655565088599854022082747
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.642852 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.642852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 1.chip_sw_clkmgr_off_otbn_trans.112605640601787548202713499420532565356954526375063310072463047211931854136603
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12018.572682 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.572682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

Test chip_rv_dm_lc_disabled has 2 failures.

1.chip_rv_dm_lc_disabled.72442171583612696708518211385231846379878198288220614813065114348431989245578
Line 251, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 24993.121473 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40490 read out mismatch
  UVM_INFO @ 24993.121473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_rv_dm_lc_disabled.14783427197187958469533057420238267674165794019205590151239578527144961826311
Line 224, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 9163.766652 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4054c read out mismatch
  UVM_INFO @ 9163.766652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 12.chip_sw_all_escalation_resets.37920726876935627607600207389455201957707892382689998368686505566632518881565
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 5956.314679 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 5956.314679 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.chip_sw_all_escalation_resets.105517449093401576309692540741661333978742091418657105199580568016258193654071
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4130.586676 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4130.586676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 54.chip_sw_all_escalation_resets.48131170959535726252275112402704104066211028014199079748056021962136896726789
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.240001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 71.chip_sw_all_escalation_resets.62821842905534437927093960685530366278531158395333663679221436377650073065372
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.180001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 1.chip_sw_rv_core_ibex_rnd.86348854374429039081209846643550784168207180196810770440052086714140132243637
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4219.245920 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4219.245920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36738) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.89813859841433200569704472572067733352385504983789529543704105033309992560455
Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3975.620728 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36738) { a_addr: 'h40648  a_data: 'h6d4adac0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h4  a_user: 'h185c8  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3975.620728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 42.chip_sw_all_escalation_resets.23494872999726367750027094007163796847109248065511585688122695200538618403920
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 12018.409158 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.409158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```