AES/MASKED Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	121.247us	1	1	100.00
V1	smoke	aes_smoke	6.000s	239.793us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	57.810us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	72.272us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	965.886us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	456.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	59.874us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	72.272us	20	20	100.00
		aes_csr_aliasing	4.000s	456.510us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	239.793us	50	50	100.00
		aes_config_error	1.283m	3.450ms	50	50	100.00
		aes_stress	15.000s	1.276ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	239.793us	50	50	100.00
		aes_config_error	1.283m	3.450ms	50	50	100.00
		aes_stress	15.000s	1.276ms	50	50	100.00
V2	back2back	aes_stress	15.000s	1.276ms	50	50	100.00
		aes_b2b	43.000s	1.293ms	50	50	100.00
V2	backpressure	aes_stress	15.000s	1.276ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	239.793us	50	50	100.00
		aes_config_error	1.283m	3.450ms	50	50	100.00
		aes_stress	15.000s	1.276ms	50	50	100.00
		aes_alert_reset	10.000s	530.799us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	131.424us	50	50	100.00
		aes_config_error	1.283m	3.450ms	50	50	100.00
		aes_alert_reset	10.000s	530.799us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	359.826us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	2.647ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	530.799us	50	50	100.00
V2	stress	aes_stress	15.000s	1.276ms	50	50	100.00
V2	sideload	aes_stress	15.000s	1.276ms	50	50	100.00
		aes_sideload	13.000s	772.131us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	1.128ms	50	50	100.00
V2	stress_all	aes_stress_all	54.000s	873.131us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	110.468us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	670.201us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	670.201us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	57.810us	5	5	100.00
		aes_csr_rw	3.000s	72.272us	20	20	100.00
		aes_csr_aliasing	4.000s	456.510us	5	5	100.00
		aes_same_csr_outstanding	3.000s	232.549us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	57.810us	5	5	100.00
		aes_csr_rw	3.000s	72.272us	20	20	100.00
		aes_csr_aliasing	4.000s	456.510us	5	5	100.00
		aes_same_csr_outstanding	3.000s	232.549us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	367.101us	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	201.863us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	529.599us	5	5	100.00
		aes_tl_intg_err	3.000s	275.766us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	275.766us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	530.799us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	239.793us	50	50	100.00
		aes_stress	15.000s	1.276ms	50	50	100.00
		aes_alert_reset	10.000s	530.799us	50	50	100.00
		aes_core_fi	33.000s	10.008ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	765.460us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	131.629us	50	50	100.00
		aes_stress	15.000s	1.276ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	1.276ms	50	50	100.00
		aes_sideload	13.000s	772.131us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	131.629us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	131.629us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	131.629us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	131.629us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	131.629us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	1.276ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	1.276ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	1.827ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	1.827ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.025ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	1.827ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	530.799us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_ctr_fi	3.000s	80.202us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	1.827ms	50	50	100.00
		aes_control_fi	48.000s	10.012ms	279	300	93.00
		aes_cipher_fi	44.000s	10.025ms	342	350	97.71
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	41.000s	949.221us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1562	1602	97.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.24	98.51	96.20	99.34	95.34	97.99	97.78	98.51	97.79

Failure Buckets

Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 14 failures.
  - 13.aes_control_fi.788557572908868836239087831032489337995468689149442509639896820160211190692
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_control_fi.25692495579728492998676522983702046922860825052785007300973343951517051041109
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 66.aes_cipher_fi.107314665237826206192301961674537090956165351630839123010984929508926979191008
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030894942 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030894942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 106.aes_cipher_fi.30908380646327739457189527633340613242648094299791403923637501999328528704320
    Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/106.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10023073872 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023073872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.50189965737234353264666919600003801341661339396293941040179722038301271631949
Line 1045, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2118647773 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2118647773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.3047902156551881241354943486778462170794966046308129856564041686721608595542
Line 329, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2577175631 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2577175631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 37.aes_control_fi.89859353689295826619353553615902695179756514108206332359495898321320794715485
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012257984 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012257984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 51.aes_control_fi.73178229697203391989640309518376915883360738488141445803531170455550144636329
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010540111 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010540111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 3.aes_stress_all_with_rand_reset.79596110133487196806777689692534975983227364955554512389754564393388301495338
    Line 566, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3064180963 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3064180963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.39543670304575398908528291847314884944657287846110190439297729231022652724397
    Line 626, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 949220626 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 949220626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 37.aes_core_fi.70479693817608915514219338739852312458393330344441804209575869643000124054065
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007633909 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007633909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```